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| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-11-01 00:06:28 +0530 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-11-05 09:41:27 +0100 |
| commit | db7548934603d9eda12649dff97ea5c29884405d (patch) | |
| tree | 044ef920f1f3751b791e7eabf5e8b823bcb441c1 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 859783d1390035e29ba850963bded2b4ffdf43b5 (diff) | |
clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
MUX bits for MMC clock register range are 25:24 where 24 is shift
and 2 is width So fix the width number from 3 to 2.
Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions