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-rw-r--r--arch/ia64/Kconfig4
-rw-r--r--arch/ia64/include/asm/pal.h2
-rw-r--r--arch/ia64/include/asm/perfmon_default_smpl.h4
-rw-r--r--arch/ia64/include/asm/sn/bte.h2
-rw-r--r--arch/ia64/include/asm/sn/shub_mmr.h2
-rw-r--r--arch/ia64/include/asm/sn/shubio.h4
-rw-r--r--arch/ia64/kernel/cyclone.c2
-rw-r--r--arch/ia64/kernel/perfmon_default_smpl.c2
-rw-r--r--arch/ia64/kernel/smpboot.c2
-rw-r--r--arch/ia64/kernel/topology.c2
-rw-r--r--arch/ia64/kvm/process.c2
-rw-r--r--arch/ia64/lib/do_csum.S2
-rw-r--r--arch/ia64/sn/kernel/irq.c6
-rw-r--r--arch/ia64/sn/kernel/sn2/sn_proc_fs.c42
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_dma.c2
15 files changed, 19 insertions, 61 deletions
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index c4ea0925cdbd..e5cc56ae6ce3 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -414,11 +414,11 @@ config PERMIT_BSP_REMOVE
support.
config FORCE_CPEI_RETARGET
- bool "Force assumption that CPEI can be re-targetted"
+ bool "Force assumption that CPEI can be re-targeted"
depends on PERMIT_BSP_REMOVE
default n
---help---
- Say Y if you need to force the assumption that CPEI can be re-targetted to
+ Say Y if you need to force the assumption that CPEI can be re-targeted to
any cpu in the system. This hint is available via ACPI 3.0 specifications.
Tiger4 systems are capable of re-directing CPEI to any CPU other than BSP.
This option it useful to enable this feature on older BIOS's as well.
diff --git a/arch/ia64/include/asm/pal.h b/arch/ia64/include/asm/pal.h
index 6a292505b396..2e69284df8e7 100644
--- a/arch/ia64/include/asm/pal.h
+++ b/arch/ia64/include/asm/pal.h
@@ -1669,7 +1669,7 @@ typedef union pal_vp_info_u {
} pal_vp_info_u_t;
/*
- * Returns infomation about virtual processor features
+ * Returns information about virtual processor features
*/
static inline s64
ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
diff --git a/arch/ia64/include/asm/perfmon_default_smpl.h b/arch/ia64/include/asm/perfmon_default_smpl.h
index 74724b24c2b7..a2d560c67230 100644
--- a/arch/ia64/include/asm/perfmon_default_smpl.h
+++ b/arch/ia64/include/asm/perfmon_default_smpl.h
@@ -67,8 +67,8 @@ typedef struct {
unsigned long ip; /* where did the overflow interrupt happened */
unsigned long tstamp; /* ar.itc when entering perfmon intr. handler */
- unsigned short cpu; /* cpu on which the overflow occured */
- unsigned short set; /* event set active when overflow ocurred */
+ unsigned short cpu; /* cpu on which the overflow occurred */
+ unsigned short set; /* event set active when overflow occurred */
int tgid; /* thread group id (for NPTL, this is getpid()) */
} pfm_default_smpl_entry_t;
diff --git a/arch/ia64/include/asm/sn/bte.h b/arch/ia64/include/asm/sn/bte.h
index 96798d2da7c2..cc6c4dbf53af 100644
--- a/arch/ia64/include/asm/sn/bte.h
+++ b/arch/ia64/include/asm/sn/bte.h
@@ -216,7 +216,7 @@ extern void bte_error_handler(unsigned long);
bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
/*
- * The following is the prefered way of calling bte_unaligned_copy
+ * The following is the preferred way of calling bte_unaligned_copy
* If the copy is fully cache line aligned, then bte_copy is
* used instead. Since bte_copy is inlined, this saves a call
* stack. NOTE: bte_copy is called synchronously and does block
diff --git a/arch/ia64/include/asm/sn/shub_mmr.h b/arch/ia64/include/asm/sn/shub_mmr.h
index 7de1d1d4b71a..a84d870f4294 100644
--- a/arch/ia64/include/asm/sn/shub_mmr.h
+++ b/arch/ia64/include/asm/sn/shub_mmr.h
@@ -459,7 +459,7 @@
/* ==================================================================== */
/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
/* and SHUB2 that it makes sense to define a geberic name for the MMR. */
-/* It is acceptible to use (for example) SH_IPI_INT to reference the */
+/* It is acceptable to use (for example) SH_IPI_INT to reference the */
/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */
/* on the type of the SHUB. Do not use these #defines in performance */
/* critical code or loops - there is a small performance penalty. */
diff --git a/arch/ia64/include/asm/sn/shubio.h b/arch/ia64/include/asm/sn/shubio.h
index 6052422a22b3..ecb8a49476b6 100644
--- a/arch/ia64/include/asm/sn/shubio.h
+++ b/arch/ia64/include/asm/sn/shubio.h
@@ -1383,7 +1383,7 @@ typedef union ii_ibcr_u {
* response is capture in IXSM and IXSS, and IXSS[VALID] is set. The *
* errant header is thereby captured, and no further spurious read *
* respones are captured until IXSS[VALID] is cleared by setting the *
- * appropriate bit in IECLR.Everytime a spurious read response is *
+ * appropriate bit in IECLR. Every time a spurious read response is *
* detected, the SPUR_RD bit of the PRB corresponding to the incoming *
* message's SIDN field is set. This always happens, regarless of *
* whether a header is captured. The programmer should check *
@@ -2738,7 +2738,7 @@ typedef union ii_ippr_u {
/************************************************************************
* *
* The following defines which were not formed into structures are *
- * probably indentical to another register, and the name of the *
+ * probably identical to another register, and the name of the *
* register is provided against each of these registers. This *
* information needs to be checked carefully *
* *
diff --git a/arch/ia64/kernel/cyclone.c b/arch/ia64/kernel/cyclone.c
index d52f1f78eff2..1b811c61bdc6 100644
--- a/arch/ia64/kernel/cyclone.c
+++ b/arch/ia64/kernel/cyclone.c
@@ -31,7 +31,7 @@ static struct clocksource clocksource_cyclone = {
.rating = 300,
.read = read_cyclone,
.mask = (1LL << 40) - 1,
- .mult = 0, /*to be caluclated*/
+ .mult = 0, /*to be calculated*/
.shift = 16,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
diff --git a/arch/ia64/kernel/perfmon_default_smpl.c b/arch/ia64/kernel/perfmon_default_smpl.c
index 5f637bbfcccd..30c644ea44c9 100644
--- a/arch/ia64/kernel/perfmon_default_smpl.c
+++ b/arch/ia64/kernel/perfmon_default_smpl.c
@@ -150,7 +150,7 @@ default_handler(struct task_struct *task, void *buf, pfm_ovfl_arg_t *arg, struct
* current = task running at the time of the overflow.
*
* per-task mode:
- * - this is ususally the task being monitored.
+ * - this is usually the task being monitored.
* Under certain conditions, it might be a different task
*
* system-wide:
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index 44f11ee411c0..14ec641003da 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -703,7 +703,7 @@ int migrate_platform_irqs(unsigned int cpu)
data->chip->irq_disable(data);
data->chip->irq_set_affinity(data, mask, false);
data->chip->irq_enable(data);
- printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu);
+ printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu);
}
}
if (!data) {
diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c
index 0baa1bbb65fe..0e0e0cc9e392 100644
--- a/arch/ia64/kernel/topology.c
+++ b/arch/ia64/kernel/topology.c
@@ -43,7 +43,7 @@ int __ref arch_register_cpu(int num)
{
#ifdef CONFIG_ACPI
/*
- * If CPEI can be re-targetted or if this is not
+ * If CPEI can be re-targeted or if this is not
* CPEI target, then it is hotpluggable
*/
if (can_cpei_retarget() || !is_cpu_cpei_target(num))
diff --git a/arch/ia64/kvm/process.c b/arch/ia64/kvm/process.c
index bb862fb224f2..b0398740b48d 100644
--- a/arch/ia64/kvm/process.c
+++ b/arch/ia64/kvm/process.c
@@ -987,7 +987,7 @@ static void vmm_sanity_check(struct kvm_vcpu *vcpu)
static void kvm_do_resume_op(struct kvm_vcpu *vcpu)
{
- vmm_sanity_check(vcpu); /*Guarantee vcpu runing on healthy vmm!*/
+ vmm_sanity_check(vcpu); /*Guarantee vcpu running on healthy vmm!*/
if (test_and_clear_bit(KVM_REQ_RESUME, &vcpu->requests)) {
vcpu_do_resume(vcpu);
diff --git a/arch/ia64/lib/do_csum.S b/arch/ia64/lib/do_csum.S
index 6bec2fc9f5b2..1a431a5cf86f 100644
--- a/arch/ia64/lib/do_csum.S
+++ b/arch/ia64/lib/do_csum.S
@@ -201,7 +201,7 @@ GLOBAL_ENTRY(do_csum)
;;
(p6) adds result1[0]=1,result1[0]
(p9) br.cond.sptk .do_csum_exit // if (count == 1) exit
- // Fall through to caluculate the checksum, feeding result1[0] as
+ // Fall through to calculate the checksum, feeding result1[0] as
// the initial value in result1[0].
//
// Calculate the checksum loading two 8-byte words per loop.
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
index 7f399f9d99c7..81a1f4e6bcd8 100644
--- a/arch/ia64/sn/kernel/irq.c
+++ b/arch/ia64/sn/kernel/irq.c
@@ -227,7 +227,7 @@ void sn_set_err_irq_affinity(unsigned int irq)
{
/*
* On systems which support CPU disabling (SHub2), all error interrupts
- * are targetted at the boot CPU.
+ * are targeted at the boot CPU.
*/
if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT))
set_irq_affinity_info(irq, cpu_physical_id(0), 0);
@@ -412,7 +412,7 @@ sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
/* Don't force an interrupt if the irq has been disabled */
- if (!irqd_irq_disabled(sn_irq_info->irq_irq) &&
+ if (!irqd_irq_disabled(irq_get_irq_data(sn_irq_info->irq_irq)) &&
pci_provider && pci_provider->force_interrupt)
(*pci_provider->force_interrupt)(sn_irq_info);
}
@@ -435,7 +435,7 @@ static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
/*
* Bridge types attached to TIO (anything but PIC) do not need this WAR
* since they do not target Shub II interrupt registers. If that
- * ever changes, this check needs to accomodate.
+ * ever changes, this check needs to accommodate.
*/
if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
return;
diff --git a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c
index c76d8dc3aea3..7aab87f48060 100644
--- a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c
+++ b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c
@@ -45,38 +45,6 @@ static int licenseID_open(struct inode *inode, struct file *file)
return single_open(file, licenseID_show, NULL);
}
-/*
- * Enable forced interrupt by default.
- * When set, the sn interrupt handler writes the force interrupt register on
- * the bridge chip. The hardware will then send an interrupt message if the
- * interrupt line is active. This mimics a level sensitive interrupt.
- */
-extern int sn_force_interrupt_flag;
-
-static int sn_force_interrupt_show(struct seq_file *s, void *p)
-{
- seq_printf(s, "Force interrupt is %s\n",
- sn_force_interrupt_flag ? "enabled" : "disabled");
- return 0;
-}
-
-static ssize_t sn_force_interrupt_write_proc(struct file *file,
- const char __user *buffer, size_t count, loff_t *data)
-{
- char val;
-
- if (copy_from_user(&val, buffer, 1))
- return -EFAULT;
-
- sn_force_interrupt_flag = (val == '0') ? 0 : 1;
- return count;
-}
-
-static int sn_force_interrupt_open(struct inode *inode, struct file *file)
-{
- return single_open(file, sn_force_interrupt_show, NULL);
-}
-
static int coherence_id_show(struct seq_file *s, void *p)
{
seq_printf(s, "%d\n", partition_coherence_id());
@@ -114,14 +82,6 @@ static const struct file_operations proc_license_id_fops = {
.release = single_release,
};
-static const struct file_operations proc_sn_force_intr_fops = {
- .open = sn_force_interrupt_open,
- .read = seq_read,
- .write = sn_force_interrupt_write_proc,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
static const struct file_operations proc_coherence_id_fops = {
.open = coherence_id_open,
.read = seq_read,
@@ -149,8 +109,6 @@ void register_sn_procfs(void)
proc_create("system_serial_number", 0444, sgi_proc_dir,
&proc_system_sn_fops);
proc_create("licenseID", 0444, sgi_proc_dir, &proc_license_id_fops);
- proc_create("sn_force_interrupt", 0644, sgi_proc_dir,
- &proc_sn_force_intr_fops);
proc_create("coherence_id", 0444, sgi_proc_dir,
&proc_coherence_id_fops);
proc_create("sn_topology", 0444, sgi_proc_dir, &proc_sn_topo_fops);
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index c659ad5613a0..33def666a664 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -227,7 +227,7 @@ pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction)
* after doing the read. For PIC this routine then forces a fake interrupt
* on another line, which is logically associated with the slot that the PIO
* is addressed to. It then spins while watching the memory location that
- * the interrupt is targetted to. When the interrupt response arrives, we
+ * the interrupt is targeted to. When the interrupt response arrives, we
* are sure that the DMA has landed in memory and it is safe for the driver
* to proceed. For TIOCP use the Device(x) Write Request Buffer Flush
* Bridge register since it ensures the data has entered the coherence domain,
generated by cgit v1.2.3-70-g09d2 (git 2.47.1) at 2024-12-25 04:38:36 +0000