diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15_common.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15_common.h | 75 |
1 files changed, 33 insertions, 42 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index 8cdf5d1685cb..14bd794bbea6 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -77,27 +77,11 @@ }) #define WREG32_RLC(reg, value) \ - do { \ - if (amdgpu_sriov_fullaccess(adev)) { \ - uint32_t i = 0; \ - uint32_t retries = 50000; \ - uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \ - uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \ - uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \ - WREG32(r0, value); \ - WREG32(r1, (reg | 0x80000000)); \ - WREG32(spare_int, 0x1); \ - for (i = 0; i < retries; i++) { \ - u32 tmp = RREG32(r1); \ - if (!(tmp & 0x80000000)) \ - break; \ - udelay(10); \ - } \ - if (i >= retries) \ - pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ - } else { \ - WREG32(reg, value); \ - } \ + do { \ + if (adev->gfx.rlc.funcs->rlcg_wreg) \ + adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, 0); \ + else \ + WREG32(reg, value); \ } while (0) #define WREG32_RLC_EX(prefix, reg, value) \ @@ -125,23 +109,24 @@ } while (0) #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ - do { \ - uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ - if (amdgpu_sriov_fullaccess(adev)) { \ - uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \ - uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \ - uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \ - uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \ - if (target_reg == grbm_cntl) \ - WREG32(r2, value); \ - else if (target_reg == grbm_idx) \ - WREG32(r3, value); \ - WREG32(target_reg, value); \ - } else { \ - WREG32(target_reg, value); \ - } \ + WREG32_RLC((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) + +#define RREG32_RLC(reg) \ + (adev->gfx.rlc.funcs->rlcg_rreg ? \ + adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, 0) : RREG32(reg)) + +#define WREG32_RLC_NO_KIQ(reg, value) \ + do { \ + if (adev->gfx.rlc.funcs->rlcg_wreg) \ + adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, AMDGPU_REGS_NO_KIQ); \ + else \ + WREG32_NO_KIQ(reg, value); \ } while (0) +#define RREG32_RLC_NO_KIQ(reg) \ + (adev->gfx.rlc.funcs->rlcg_rreg ? \ + adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, AMDGPU_REGS_NO_KIQ) : RREG32_NO_KIQ(reg)) + #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ do { \ uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ @@ -160,10 +145,13 @@ } \ } while (0) +#define RREG32_SOC15_RLC(ip, inst, reg) \ + RREG32_RLC(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + #define WREG32_SOC15_RLC(ip, inst, reg, value) \ do { \ - uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ - WREG32_RLC(target_reg, value); \ + uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\ + WREG32_RLC(target_reg, value); \ } while (0) #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ @@ -173,11 +161,14 @@ } while (0) #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ - WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ - (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) + WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ + (RREG32_RLC(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ + & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ - WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value) + WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value) + +#define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \ + RREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)) #endif |