diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 36 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 116 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 28 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 32 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vi.c | 22 |
12 files changed, 162 insertions, 160 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index e0668173fc1a..837cdd2a6a2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -681,8 +681,8 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) result = AMDGPU_UCODE_ID_CP_MEC1; break; case CGS_UCODE_ID_CP_MEC_JT2: - if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_BAFFIN - || adev->asic_type == CHIP_ELLESMERE) + if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11 + || adev->asic_type == CHIP_POLARIS10) result = AMDGPU_UCODE_ID_CP_MEC2; else result = AMDGPU_UCODE_ID_CP_MEC1; @@ -742,17 +742,17 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, case CHIP_FIJI: strcpy(fw_name, "amdgpu/fiji_smc.bin"); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: if (type == CGS_UCODE_ID_SMU) - strcpy(fw_name, "amdgpu/baffin_smc.bin"); + strcpy(fw_name, "amdgpu/polaris11_smc.bin"); else if (type == CGS_UCODE_ID_SMU_SK) - strcpy(fw_name, "amdgpu/baffin_smc_sk.bin"); + strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin"); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: if (type == CGS_UCODE_ID_SMU) - strcpy(fw_name, "amdgpu/ellesmere_smc.bin"); + strcpy(fw_name, "amdgpu/polaris10_smc.bin"); else if (type == CGS_UCODE_ID_SMU_SK) - strcpy(fw_name, "amdgpu/ellesmere_smc_sk.bin"); + strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin"); break; default: DRM_ERROR("SMC firmware not supported\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 52245c4c6d65..14e832fe83db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -59,8 +59,8 @@ static const char *amdgpu_asic_name[] = { "FIJI", "CARRIZO", "STONEY", - "ELLESMERE", - "BAFFIN", + "POLARIS10", + "POLARIS11", "LAST", }; @@ -1148,8 +1148,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) case CHIP_TOPAZ: case CHIP_TONGA: case CHIP_FIJI: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: case CHIP_CARRIZO: case CHIP_STONEY: if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e11b1f2982d6..b48942a1e567 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -277,16 +277,16 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, /* stoney */ {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, - /* Baffin */ - {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - /* Ellesmere */ - {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE}, - {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE}, + /* Polaris11 */ + {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + /* Polaris10 */ + {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, + {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0, 0, 0} }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index ea2006a768eb..f315995e931e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -99,10 +99,12 @@ static int amdgpu_pp_early_init(void *handle) #ifdef CONFIG_DRM_AMD_POWERPLAY switch (adev->asic_type) { + case CHIP_POLARIS11: + case CHIP_POLARIS10: + adev->pp_enabled = true; + break; case CHIP_TONGA: case CHIP_FIJI: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true; break; case CHIP_CARRIZO: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 9599bc6484b4..cf01137fe6e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -54,8 +54,8 @@ #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" -#define FIRMWARE_ELLESMERE "amdgpu/ellesmere_uvd.bin" -#define FIRMWARE_BAFFIN "amdgpu/baffin_uvd.bin" +#define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" +#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" /** * amdgpu_uvd_cs_ctx - Command submission parser context @@ -87,8 +87,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); MODULE_FIRMWARE(FIRMWARE_STONEY); -MODULE_FIRMWARE(FIRMWARE_ELLESMERE); -MODULE_FIRMWARE(FIRMWARE_BAFFIN); +MODULE_FIRMWARE(FIRMWARE_POLARIS10); +MODULE_FIRMWARE(FIRMWARE_POLARIS11); static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); static void amdgpu_uvd_idle_work_handler(struct work_struct *work); @@ -135,11 +135,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break; - case CHIP_ELLESMERE: - fw_name = FIRMWARE_ELLESMERE; + case CHIP_POLARIS10: + fw_name = FIRMWARE_POLARIS10; break; - case CHIP_BAFFIN: - fw_name = FIRMWARE_BAFFIN; + case CHIP_POLARIS11: + fw_name = FIRMWARE_POLARIS11; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 66d5f7fee485..80c1048f3324 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -50,8 +50,8 @@ #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin" #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin" -#define FIRMWARE_ELLESMERE "amdgpu/ellesmere_vce.bin" -#define FIRMWARE_BAFFIN "amdgpu/baffin_vce.bin" +#define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin" +#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin" #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); @@ -64,8 +64,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); MODULE_FIRMWARE(FIRMWARE_STONEY); -MODULE_FIRMWARE(FIRMWARE_ELLESMERE); -MODULE_FIRMWARE(FIRMWARE_BAFFIN); +MODULE_FIRMWARE(FIRMWARE_POLARIS10); +MODULE_FIRMWARE(FIRMWARE_POLARIS11); static void amdgpu_vce_idle_work_handler(struct work_struct *work); @@ -117,11 +117,11 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break; - case CHIP_ELLESMERE: - fw_name = FIRMWARE_ELLESMERE; + case CHIP_POLARIS10: + fw_name = FIRMWARE_POLARIS10; break; - case CHIP_BAFFIN: - fw_name = FIRMWARE_BAFFIN; + case CHIP_POLARIS11: + fw_name = FIRMWARE_POLARIS11; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 61afc5eab1b5..d28873c5f5b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -132,7 +132,7 @@ static const u32 stoney_golden_settings_a11[] = mmFBC_MISC, 0x1f311fff, 0x14302000, }; -static const u32 baffin_golden_settings_a11[] = +static const u32 polaris11_golden_settings_a11[] = { mmDCI_CLK_CNTL, 0x00000080, 0x00000000, mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, @@ -141,7 +141,7 @@ static const u32 baffin_golden_settings_a11[] = mmHDMI_CONTROL, 0x313f031f, 0x00000011, }; -static const u32 ellesmere_golden_settings_a11[] = +static const u32 polaris10_golden_settings_a11[] = { mmDCI_CLK_CNTL, 0x00000080, 0x00000000, mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, @@ -165,15 +165,15 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) stoney_golden_settings_a11, (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - baffin_golden_settings_a11, - (const u32)ARRAY_SIZE(baffin_golden_settings_a11)); + polaris11_golden_settings_a11, + (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - ellesmere_golden_settings_a11, - (const u32)ARRAY_SIZE(ellesmere_golden_settings_a11)); + polaris10_golden_settings_a11, + (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); break; default: break; @@ -1611,10 +1611,10 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev) case CHIP_STONEY: adev->mode_info.audio.num_pins = 7; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->mode_info.audio.num_pins = 8; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->mode_info.audio.num_pins = 6; break; default: @@ -2411,8 +2411,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) u32 pll_in_use; int pll; - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(amdgpu_crtc->encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; @@ -2838,8 +2838,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, if (!amdgpu_crtc->adjusted_clock) return -EINVAL; - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(amdgpu_crtc->encoder); int encoder_mode = @@ -3004,12 +3004,12 @@ static int dce_v11_0_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; @@ -3116,8 +3116,8 @@ static int dce_v11_0_hw_init(void *handle) /* init dig PHYs, disp eng pll */ amdgpu_atombios_crtc_powergate_init(adev); amdgpu_atombios_encoder_init_dig(adev); - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); amdgpu_atombios_crtc_set_dce_clock(adev, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 651edc1b1a6d..6be83f183f16 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -52,7 +52,7 @@ #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 -#define BAFFIN_GB_ADDR_CONFIG_GOLDEN 0x22011002 +#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) @@ -121,19 +121,19 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); -MODULE_FIRMWARE("amdgpu/baffin_ce.bin"); -MODULE_FIRMWARE("amdgpu/baffin_pfp.bin"); -MODULE_FIRMWARE("amdgpu/baffin_me.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mec.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mec2.bin"); -MODULE_FIRMWARE("amdgpu/baffin_rlc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_ce.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_pfp.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_me.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mec.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mec2.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_rlc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = { @@ -265,7 +265,7 @@ static const u32 tonga_mgcg_cgcg_init[] = mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, mmDB_DEBUG2, 0xf00fffff, 0x00000400, @@ -281,7 +281,7 @@ static const u32 golden_settings_baffin_a11[] = mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, }; -static const u32 baffin_golden_common_all[] = +static const u32 polaris11_golden_common_all[] = { mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, @@ -293,7 +293,7 @@ static const u32 baffin_golden_common_all[] = mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, @@ -311,7 +311,7 @@ static const u32 golden_settings_ellesmere_a11[] = mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, }; -static const u32 ellesmere_golden_common_all[] = +static const u32 polaris10_golden_common_all[] = { mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, @@ -674,21 +674,21 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) tonga_golden_common_all, (const u32)ARRAY_SIZE(tonga_golden_common_all)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); amdgpu_program_register_sequence(adev, - baffin_golden_common_all, - (const u32)ARRAY_SIZE(baffin_golden_common_all)); + polaris11_golden_common_all, + (const u32)ARRAY_SIZE(polaris11_golden_common_all)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); amdgpu_program_register_sequence(adev, - ellesmere_golden_common_all, - (const u32)ARRAY_SIZE(ellesmere_golden_common_all)); + polaris10_golden_common_all, + (const u32)ARRAY_SIZE(polaris10_golden_common_all)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -859,11 +859,11 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_STONEY: chip_name = "stoney"; @@ -1092,11 +1092,11 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TONGA: - case CHIP_ELLESMERE: + case CHIP_POLARIS10: buffer[count++] = cpu_to_le32(0x16000012); buffer[count++] = cpu_to_le32(0x0000002A); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: buffer[count++] = cpu_to_le32(0x16000012); buffer[count++] = cpu_to_le32(0x00000000); break; @@ -1628,7 +1628,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: ret = amdgpu_atombios_get_gfx_info(adev); if (ret) return ret; @@ -1640,9 +1640,9 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.sc_prim_fifo_size_backend = 0x100; adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; - gb_addr_config = BAFFIN_GB_ADDR_CONFIG_GOLDEN; + gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: ret = amdgpu_atombios_get_gfx_info(adev); if (ret) return ret; @@ -2551,7 +2551,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | @@ -2753,7 +2753,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | @@ -3658,7 +3658,7 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev) WREG32(mmRLC_SRM_CNTL, data); } -static void baffin_init_power_gating(struct amdgpu_device *adev) +static void polaris11_init_power_gating(struct amdgpu_device *adev) { uint32_t data; @@ -3701,8 +3701,8 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev) gfx_v8_0_init_save_restore_list(adev); gfx_v8_0_enable_save_restore_machine(adev); - if (adev->asic_type == CHIP_BAFFIN) - baffin_init_power_gating(adev); + if (adev->asic_type == CHIP_POLARIS11) + polaris11_init_power_gating(adev); } } @@ -3776,8 +3776,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) /* disable CG */ WREG32(mmRLC_CGCG_CGLS_CTRL, 0); - if (adev->asic_type == CHIP_BAFFIN || - adev->asic_type == CHIP_ELLESMERE) + if (adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10) WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0); /* disable PG */ @@ -3958,11 +3958,11 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TONGA: - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_ring_write(ring, 0x16000012); amdgpu_ring_write(ring, 0x0000002A); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_ring_write(ring, 0x16000012); amdgpu_ring_write(ring, 0x00000000); break; @@ -4610,8 +4610,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) if ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_FIJI) || (adev->asic_type == CHIP_STONEY) || - (adev->asic_type == CHIP_BAFFIN) || - (adev->asic_type == CHIP_ELLESMERE)) { + (adev->asic_type == CHIP_POLARIS11) || + (adev->asic_type == CHIP_POLARIS10)) { WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2); WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, @@ -4646,8 +4646,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); mqd->cp_hqd_persistent_state = tmp; if (adev->asic_type == CHIP_STONEY || - adev->asic_type == CHIP_BAFFIN || - adev->asic_type == CHIP_ELLESMERE) { + adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10) { tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL); tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1); WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp); @@ -5216,7 +5216,7 @@ static int gfx_v8_0_late_init(void *handle) return 0; } -static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5242,7 +5242,7 @@ static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, } } -static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5263,7 +5263,7 @@ static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev } } -static void baffin_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5293,15 +5293,15 @@ static int gfx_v8_0_set_powergating_state(void *handle, return 0; switch (adev->asic_type) { - case CHIP_BAFFIN: - if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG) - baffin_enable_gfx_static_mg_power_gating(adev, + case CHIP_POLARIS11: + if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) + polaris11_enable_gfx_static_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); - else if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG) - baffin_enable_gfx_dynamic_mg_power_gating(adev, + else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) + polaris11_enable_gfx_dynamic_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); else - baffin_enable_gfx_quick_mg_power_gating(adev, + polaris11_enable_gfx_quick_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index cf1f6680b55c..e6715ec2489f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -43,8 +43,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mc.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); static const u32 golden_settings_tonga_a11[] = { @@ -75,7 +75,7 @@ static const u32 fiji_mgcg_cgcg_init[] = mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, @@ -83,7 +83,7 @@ static const u32 golden_settings_baffin_a11[] = mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, @@ -122,15 +122,15 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -238,11 +238,11 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_TONGA: chip_name = "tonga"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_FIJI: case CHIP_CARRIZO: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 79e5fd018a11..1b5053f9b120 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -56,10 +56,10 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_sdma.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_sdma1.bin"); -MODULE_FIRMWARE("amdgpu/baffin_sdma.bin"); -MODULE_FIRMWARE("amdgpu/baffin_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = @@ -106,7 +106,7 @@ static const u32 fiji_mgcg_cgcg_init[] = mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -118,7 +118,7 @@ static const u32 golden_settings_baffin_a11[] = mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, @@ -203,15 +203,15 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -261,11 +261,11 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_CARRIZO: chip_name = "carrizo"; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index c12fd832c884..58342853b69c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -315,11 +315,11 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) { u32 tmp; - /* Fiji, Stoney, Ellesmere, Baffin are single pipe */ + /* Fiji, Stoney, Polaris10, Polaris11 are single pipe */ if ((adev->asic_type == CHIP_FIJI) || (adev->asic_type == CHIP_STONEY) || - (adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) + (adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) return AMDGPU_VCE_HARVEST_VCE1; /* Tonga and CZ are dual or single pipe */ diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index ae78bd41db7b..2c228d6c672e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -276,8 +276,8 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) stoney_mgcg_cgcg_init, (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: default: break; } @@ -539,8 +539,8 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, break; case CHIP_FIJI: case CHIP_TONGA: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: case CHIP_CARRIZO: case CHIP_STONEY: asic_register_table = cz_allowed_read_registers; @@ -911,7 +911,7 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] = }, }; -static const struct amdgpu_ip_block_version baffin_ip_blocks[] = +static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = { /* ORDER MATTERS! */ { @@ -1071,10 +1071,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) adev->ip_blocks = tonga_ip_blocks; adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: - adev->ip_blocks = baffin_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(baffin_ip_blocks); + case CHIP_POLARIS11: + case CHIP_POLARIS10: + adev->ip_blocks = polaris11_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks); break; case CHIP_CARRIZO: case CHIP_STONEY: @@ -1177,12 +1177,12 @@ static int vi_common_early_init(void *handle) adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x14; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->cg_flags = 0; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x5A; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->cg_flags = 0; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x50; |