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path: root/drivers/gpu/drm/amd/display/dc/calcs
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/calcs')
-rw-r--r--drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 00961bc37200..4486121e3986 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -987,7 +987,15 @@ bool dcn_validate_bandwidth(
if (pipe->surface) {
struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
- if (v->dpp_per_plane[input_idx] == 2) {
+ if (v->dpp_per_plane[input_idx] == 2 ||
+ ((pipe->stream->public.view_format ==
+ VIEW_3D_FORMAT_SIDE_BY_SIDE ||
+ pipe->stream->public.view_format ==
+ VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
+ (pipe->stream->public.timing.timing_3d_format ==
+ TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
+ pipe->stream->public.timing.timing_3d_format ==
+ TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
/* update previously split pipe */
hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];