diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 933b32c5760b..40ce07d2cd55 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -539,7 +539,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) int pixel_size = crtc->primary->fb->bits_per_pixel / 8; int clock; - adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; clock = adjusted_mode->crtc_clock; /* Display SR */ @@ -608,7 +608,7 @@ static bool g4x_compute_wm0(struct drm_device *dev, return false; } - adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; clock = adjusted_mode->crtc_clock; htotal = adjusted_mode->crtc_htotal; hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; @@ -695,7 +695,7 @@ static bool g4x_compute_srwm(struct drm_device *dev, } crtc = intel_get_crtc_for_plane(dev, plane); - adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; clock = adjusted_mode->crtc_clock; htotal = adjusted_mode->crtc_htotal; hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; @@ -729,7 +729,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc, { struct drm_device *dev = crtc->dev; int entries; - int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; + int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock; if (WARN(clock == 0, "Pixel clock is zero!\n")) return false; @@ -1059,7 +1059,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) /* self-refresh has much higher latency */ static const int sr_latency_ns = 12000; const struct drm_display_mode *adjusted_mode = - &to_intel_crtc(crtc)->config.adjusted_mode; + &to_intel_crtc(crtc)->config.base.adjusted_mode; int clock = adjusted_mode->crtc_clock; int htotal = adjusted_mode->crtc_htotal; int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; @@ -1144,7 +1144,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) if (IS_GEN2(dev)) cpp = 4; - adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, wm_info, fifo_size, cpp, pessimal_latency_ns); @@ -1166,7 +1166,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) if (IS_GEN2(dev)) cpp = 4; - adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, wm_info, fifo_size, cpp, pessimal_latency_ns); @@ -1205,7 +1205,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) /* self-refresh has much higher latency */ static const int sr_latency_ns = 6000; const struct drm_display_mode *adjusted_mode = - &to_intel_crtc(enabled)->config.adjusted_mode; + &to_intel_crtc(enabled)->config.base.adjusted_mode; int clock = adjusted_mode->crtc_clock; int htotal = adjusted_mode->crtc_htotal; int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; @@ -1261,7 +1261,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc) if (crtc == NULL) return; - adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; + adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode; planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, &i845_wm_info, dev_priv->display.get_fifo_size(dev, 0), @@ -1280,7 +1280,7 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); uint32_t pixel_rate; - pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; + pixel_rate = intel_crtc->config.base.adjusted_mode.crtc_clock; /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to * adjust the pixel_rate here. */ @@ -1643,7 +1643,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; + struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode; u32 linetime, ips_linetime; if (!intel_crtc_active(crtc)) @@ -1903,7 +1903,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc, return; p->active = true; - p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; + p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal; p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; p->cur.bytes_per_pixel = 4; @@ -2559,7 +2559,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) { /* TODO: Take into account the scalers once we support them */ - return config->adjusted_mode.crtc_clock; + return config->base.adjusted_mode.crtc_clock; } /* @@ -2647,7 +2647,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, p->active = intel_crtc_active(crtc); if (p->active) { - p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; + p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal; p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config); /* |