diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1')
32 files changed, 555 insertions, 2279 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index cdec3fbe6ff4..d2457490930b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -22,165 +22,20 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx) struct dpu_kms *dpu_kms = arg; struct dpu_irq *irq_obj = &dpu_kms->irq_obj; struct dpu_irq_callback *cb; - unsigned long irq_flags; - pr_debug("irq_idx=%d\n", irq_idx); + VERB("irq_idx=%d\n", irq_idx); - if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) { - DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx, - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); - } + if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) + DRM_ERROR("no registered cb, idx:%d\n", irq_idx); atomic_inc(&irq_obj->irq_counts[irq_idx]); /* * Perform registered function callback */ - spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); list_for_each_entry(cb, &irq_obj->irq_cb_tbl[irq_idx], list) if (cb->func) cb->func(cb->arg, irq_idx); - spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); - - /* - * Clear pending interrupt status in HW. - * NOTE: dpu_core_irq_callback_handler is protected by top-level - * spinlock, so it is safe to clear any interrupt status here. - */ - dpu_kms->hw_intr->ops.clear_intr_status_nolock( - dpu_kms->hw_intr, - irq_idx); -} - -int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms, - enum dpu_intr_type intr_type, u32 instance_idx) -{ - if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup) - return -EINVAL; - - return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr, - intr_type, instance_idx); -} - -/** - * _dpu_core_irq_enable - enable core interrupt given by the index - * @dpu_kms: Pointer to dpu kms context - * @irq_idx: interrupt index - */ -static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx) -{ - unsigned long irq_flags; - int ret = 0, enable_count; - - if (!dpu_kms->hw_intr || - !dpu_kms->irq_obj.enable_counts || - !dpu_kms->irq_obj.irq_counts) { - DPU_ERROR("invalid params\n"); - return -EINVAL; - } - - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) { - DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx); - return -EINVAL; - } - - enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); - DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); - trace_dpu_core_irq_enable_idx(irq_idx, enable_count); - - if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) { - ret = dpu_kms->hw_intr->ops.enable_irq( - dpu_kms->hw_intr, - irq_idx); - if (ret) - DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n", - irq_idx); - - DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret); - - spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); - /* empty callback list but interrupt is enabled */ - if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) - DPU_ERROR("irq_idx=%d enabled with no callback\n", - irq_idx); - spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); - } - - return ret; -} - -int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) -{ - int i, ret = 0, counts; - - if (!irq_idxs || !irq_count) { - DPU_ERROR("invalid params\n"); - return -EINVAL; - } - - counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]); - if (counts) - DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts); - - for (i = 0; (i < irq_count) && !ret; i++) - ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]); - - return ret; -} - -/** - * _dpu_core_irq_disable - disable core interrupt given by the index - * @dpu_kms: Pointer to dpu kms context - * @irq_idx: interrupt index - */ -static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx) -{ - int ret = 0, enable_count; - - if (!dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) { - DPU_ERROR("invalid params\n"); - return -EINVAL; - } - - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) { - DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx); - return -EINVAL; - } - - enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); - DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); - trace_dpu_core_irq_disable_idx(irq_idx, enable_count); - - if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) { - ret = dpu_kms->hw_intr->ops.disable_irq( - dpu_kms->hw_intr, - irq_idx); - if (ret) - DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n", - irq_idx); - DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret); - } - - return ret; -} - -int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) -{ - int i, ret = 0, counts; - - if (!irq_idxs || !irq_count) { - DPU_ERROR("invalid params\n"); - return -EINVAL; - } - - counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]); - if (counts == 2) - DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts); - - for (i = 0; (i < irq_count) && !ret; i++) - ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]); - - return ret; } u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear) @@ -217,19 +72,28 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx, return -EINVAL; } - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) { + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) { DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx); return -EINVAL; } - DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); + VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); - spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); + irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr); trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb); list_del_init(®ister_irq_cb->list); list_add_tail(®ister_irq_cb->list, &dpu_kms->irq_obj.irq_cb_tbl[irq_idx]); - spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); + if (list_is_first(®ister_irq_cb->list, + &dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) { + int ret = dpu_kms->hw_intr->ops.enable_irq_locked( + dpu_kms->hw_intr, + irq_idx); + if (ret) + DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n", + irq_idx); + } + dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags); return 0; } @@ -252,21 +116,27 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx, return -EINVAL; } - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) { + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) { DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx); return -EINVAL; } - DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); + VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); - spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); + irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr); trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb); list_del_init(®ister_irq_cb->list); /* empty callback list but interrupt is still enabled */ - if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) && - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])) - DPU_ERROR("irq_idx=%d enabled with no callback\n", irq_idx); - spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); + if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) { + int ret = dpu_kms->hw_intr->ops.disable_irq_locked( + dpu_kms->hw_intr, + irq_idx); + if (ret) + DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n", + irq_idx); + VERB("irq_idx=%d ret=%d\n", irq_idx, ret); + } + dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags); return 0; } @@ -290,26 +160,26 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms) #ifdef CONFIG_DEBUG_FS static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v) { - struct dpu_irq *irq_obj = s->private; + struct dpu_kms *dpu_kms = s->private; + struct dpu_irq *irq_obj = &dpu_kms->irq_obj; struct dpu_irq_callback *cb; unsigned long irq_flags; - int i, irq_count, enable_count, cb_count; + int i, irq_count, cb_count; - if (WARN_ON(!irq_obj->enable_counts || !irq_obj->irq_cb_tbl)) + if (WARN_ON(!irq_obj->irq_cb_tbl)) return 0; for (i = 0; i < irq_obj->total_irqs; i++) { - spin_lock_irqsave(&irq_obj->cb_lock, irq_flags); + irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr); cb_count = 0; irq_count = atomic_read(&irq_obj->irq_counts[i]); - enable_count = atomic_read(&irq_obj->enable_counts[i]); list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list) cb_count++; - spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags); + dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags); - if (irq_count || enable_count || cb_count) - seq_printf(s, "idx:%d irq:%d enable:%d cb:%d\n", - i, irq_count, enable_count, cb_count); + if (irq_count || cb_count) + seq_printf(s, "idx:%d irq:%d cb:%d\n", + i, irq_count, cb_count); } return 0; @@ -320,7 +190,7 @@ DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_core_irq); void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, struct dentry *parent) { - debugfs_create_file("core_irq", 0600, parent, &dpu_kms->irq_obj, + debugfs_create_file("core_irq", 0600, parent, dpu_kms, &dpu_debugfs_core_irq_fops); } #endif @@ -334,19 +204,14 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms) dpu_disable_all_irqs(dpu_kms); pm_runtime_put_sync(&dpu_kms->pdev->dev); - spin_lock_init(&dpu_kms->irq_obj.cb_lock); - /* Create irq callbacks for all possible irq_idx */ - dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size; + dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs; dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs, sizeof(struct list_head), GFP_KERNEL); - dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs, - sizeof(atomic_t), GFP_KERNEL); dpu_kms->irq_obj.irq_counts = kcalloc(dpu_kms->irq_obj.total_irqs, sizeof(atomic_t), GFP_KERNEL); for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) { INIT_LIST_HEAD(&dpu_kms->irq_obj.irq_cb_tbl[i]); - atomic_set(&dpu_kms->irq_obj.enable_counts[i], 0); atomic_set(&dpu_kms->irq_obj.irq_counts[i], 0); } } @@ -357,8 +222,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) pm_runtime_get_sync(&dpu_kms->pdev->dev); for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) - if (atomic_read(&dpu_kms->irq_obj.enable_counts[i]) || - !list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i])) + if (!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i])) DPU_ERROR("irq_idx=%d still enabled/registered\n", i); dpu_clear_all_irqs(dpu_kms); @@ -366,10 +230,8 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) pm_runtime_put_sync(&dpu_kms->pdev->dev); kfree(dpu_kms->irq_obj.irq_cb_tbl); - kfree(dpu_kms->irq_obj.enable_counts); kfree(dpu_kms->irq_obj.irq_counts); dpu_kms->irq_obj.irq_cb_tbl = NULL; - dpu_kms->irq_obj.enable_counts = NULL; dpu_kms->irq_obj.irq_counts = NULL; dpu_kms->irq_obj.total_irqs = 0; } @@ -377,21 +239,13 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) { /* - * Read interrupt status from all sources. Interrupt status are - * stored within hw_intr. - * Function will also clear the interrupt status after reading. - * Individual interrupt status bit will only get stored if it - * is enabled. - */ - dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr); - - /* * Dispatch to HW driver to handle interrupt lookup that is being * fired. When matching interrupt is located, HW driver will call to * dpu_core_irq_callback_handler with the irq_idx from the lookup table. * dpu_core_irq_callback_handler will perform the registered function * callback, and do the interrupt status clearing once the registered * callback is finished. + * Function will also clear the interrupt status after reading. */ dpu_kms->hw_intr->ops.dispatch_irqs( dpu_kms->hw_intr, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h index e30775e6585b..90ae6c9ccc95 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h @@ -30,49 +30,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms); irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms); /** - * dpu_core_irq_idx_lookup - IRQ helper function for lookup irq_idx from HW - * interrupt mapping table. - * @dpu_kms: DPU handle - * @intr_type: DPU HW interrupt type for lookup - * @instance_idx: DPU HW block instance defined in dpu_hw_mdss.h - * @return: irq_idx or -EINVAL when fail to lookup - */ -int dpu_core_irq_idx_lookup( - struct dpu_kms *dpu_kms, - enum dpu_intr_type intr_type, - uint32_t instance_idx); - -/** - * dpu_core_irq_enable - IRQ helper function for enabling one or more IRQs - * @dpu_kms: DPU handle - * @irq_idxs: Array of irq index - * @irq_count: Number of irq_idx provided in the array - * @return: 0 for success enabling IRQ, otherwise failure - * - * This function increments count on each enable and decrements on each - * disable. Interrupts is enabled if count is 0 before increment. - */ -int dpu_core_irq_enable( - struct dpu_kms *dpu_kms, - int *irq_idxs, - uint32_t irq_count); - -/** - * dpu_core_irq_disable - IRQ helper function for disabling one of more IRQs - * @dpu_kms: DPU handle - * @irq_idxs: Array of irq index - * @irq_count: Number of irq_idx provided in the array - * @return: 0 for success disabling IRQ, otherwise failure - * - * This function increments count on each enable and decrements on each - * disable. Interrupts is disabled if count is 0 after decrement. - */ -int dpu_core_irq_disable( - struct dpu_kms *dpu_kms, - int *irq_idxs, - uint32_t irq_count); - -/** * dpu_core_irq_read - IRQ helper function for reading IRQ status * @dpu_kms: DPU handle * @irq_idx: irq index diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 7cba5bbdf4b7..60fe06018581 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -132,7 +132,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state); } - DPU_DEBUG( + DRM_DEBUG_ATOMIC( "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n", crtc->base.id, perf->core_clk_rate, perf->max_per_pipe_ib, perf->bw_ctl); @@ -178,7 +178,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, struct dpu_crtc_state *tmp_cstate = to_dpu_crtc_state(tmp_crtc->state); - DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n", + DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n", tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl, tmp_cstate->bw_control); @@ -187,11 +187,11 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, /* convert bandwidth to kb */ bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000); - DPU_DEBUG("calculated bandwidth=%uk\n", bw); + DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw); threshold = kms->catalog->perf.max_bw_high; - DPU_DEBUG("final threshold bw limit = %d\n", threshold); + DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold); if (!threshold) { DPU_ERROR("no bandwidth limits specified\n"); @@ -228,7 +228,7 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, perf.bw_ctl += dpu_cstate->new_perf.bw_ctl; - DPU_DEBUG("crtc=%d bw=%llu paths:%d\n", + DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n", tmp_crtc->base.id, dpu_cstate->new_perf.bw_ctl, kms->num_paths); } @@ -278,7 +278,7 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) /* Release the bandwidth */ if (kms->perf.enable_bw_release) { trace_dpu_cmd_release_bw(crtc->base.id); - DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id); + DRM_DEBUG_ATOMIC("Release BW crtc=%d\n", crtc->base.id); dpu_crtc->cur_perf.bw_ctl = 0; _dpu_core_perf_crtc_update_bus(kms, crtc); } @@ -314,7 +314,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) clk_rate = kms->perf.fix_core_clk_rate; - DPU_DEBUG("clk:%llu\n", clk_rate); + DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate); return clk_rate; } @@ -344,7 +344,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, dpu_crtc = to_dpu_crtc(crtc); dpu_cstate = to_dpu_crtc_state(crtc->state); - DPU_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n", + DRM_DEBUG_ATOMIC("crtc:%d stop_req:%d core_clk:%llu\n", crtc->base.id, stop_req, kms->perf.core_clk_rate); old = &dpu_crtc->cur_perf; @@ -362,7 +362,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, (new->max_per_pipe_ib > old->max_per_pipe_ib))) || (!params_changed && ((new->bw_ctl < old->bw_ctl) || (new->max_per_pipe_ib < old->max_per_pipe_ib)))) { - DPU_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n", + DRM_DEBUG_ATOMIC("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n", crtc->base.id, params_changed, new->bw_ctl, old->bw_ctl); old->bw_ctl = new->bw_ctl; @@ -378,7 +378,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, update_clk = true; } } else { - DPU_DEBUG("crtc=%d disable\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc=%d disable\n", crtc->base.id); memset(old, 0, sizeof(*old)); update_bus = true; update_clk = true; @@ -413,7 +413,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, } kms->perf.core_clk_rate = clk_rate; - DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate); + DRM_DEBUG_ATOMIC("update clk rate = %lld HZ\n", clk_rate); } return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 18bc76b7f1a3..9a5c70c87cc8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -57,8 +57,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc) { struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - DPU_DEBUG("\n"); - if (!crtc) return; @@ -163,7 +161,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, lm->ops.setup_blend_config(lm, pstate->stage, 0xFF, 0, blend_op); - DPU_DEBUG("format:%p4cc, alpha_en:%u blend_op:0x%x\n", + DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n", &format->base.pixel_format, format->alpha_enable, blend_op); } @@ -220,7 +218,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); set_bit(dpu_plane_pipe(plane), fetch_active); - DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", + + DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", crtc->base.id, pstate->stage, plane->base.id, @@ -278,7 +277,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_hw_mixer *lm; int i; - DPU_DEBUG("%s\n", dpu_crtc->name); + DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); for (i = 0; i < cstate->num_mixers; i++) { mixer[i].mixer_op_mode = 0; @@ -305,7 +304,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) /* stage config flush mask */ ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); - DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", + DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", mixer[i].hw_lm->idx - LM_0, mixer[i].mixer_op_mode, ctl->idx - CTL_0, @@ -388,7 +387,7 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) DPU_ATRACE_BEGIN("crtc_frame_event"); - DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, + DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, ktime_to_ns(fevent->ts)); if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE @@ -407,9 +406,6 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) fevent->event); } - if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE) - dpu_core_perf_crtc_update(crtc, 0, false); - if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE | DPU_ENCODER_FRAME_EVENT_ERROR)) frame_done = true; @@ -477,6 +473,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event) void dpu_crtc_complete_commit(struct drm_crtc *crtc) { trace_dpu_crtc_complete_commit(DRMID(crtc)); + dpu_core_perf_crtc_update(crtc, 0, false); _dpu_crtc_complete_flip(crtc); } @@ -558,7 +555,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) /* stage config flush mask */ ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); - DPU_DEBUG("lm %d, ctl %d, flush mask 0x%x\n", + DRM_DEBUG_ATOMIC("lm %d, ctl %d, flush mask 0x%x\n", mixer[i].hw_lm->idx - DSPP_0, ctl->idx - CTL_0, mixer[i].flush_mask); @@ -572,12 +569,12 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_encoder *encoder; if (!crtc->state->enable) { - DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", + DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n", crtc->base.id, crtc->state->enable); return; } - DPU_DEBUG("crtc%d\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); _dpu_crtc_setup_lm_bounds(crtc, crtc->state); @@ -617,12 +614,12 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, struct dpu_crtc_state *cstate; if (!crtc->state->enable) { - DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", + DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n", crtc->base.id, crtc->state->enable); return; } - DPU_DEBUG("crtc%d\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); dpu_crtc = to_dpu_crtc(crtc); cstate = to_dpu_crtc_state(crtc->state); @@ -675,7 +672,7 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc, { struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); - DPU_DEBUG("crtc%d\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); __drm_atomic_helper_crtc_destroy_state(state); @@ -688,7 +685,7 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) int ret, rc = 0; if (!atomic_read(&dpu_crtc->frame_pending)) { - DPU_DEBUG("no frames pending\n"); + DRM_DEBUG_ATOMIC("no frames pending\n"); return 0; } @@ -731,9 +728,9 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { /* acquire bandwidth and other resources */ - DPU_DEBUG("crtc%d first commit\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id); } else - DPU_DEBUG("crtc%d commit\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id); dpu_crtc->play_count++; @@ -908,7 +905,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); if (!crtc_state->enable || !crtc_state->active) { - DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", + DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, crtc_state->active); memset(&cstate->new_perf, 0, sizeof(cstate->new_perf)); @@ -916,7 +913,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } mode = &crtc_state->adjusted_mode; - DPU_DEBUG("%s: check\n", dpu_crtc->name); + DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name); /* force a full mode set if active state changed */ if (crtc_state->active_changed) @@ -1024,7 +1021,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; - DPU_DEBUG("%s: zpos %d\n", dpu_crtc->name, z_pos); + DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); } for (i = 0; i < multirect_count; i++) { @@ -1376,6 +1373,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, /* initialize event handling */ spin_lock_init(&dpu_crtc->event_lock); - DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name); + DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name); return crtc; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 8d942052db8a..1c04b7cce43e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark <robdclark@gmail.com> */ @@ -26,14 +26,15 @@ #include "dpu_crtc.h" #include "dpu_trace.h" #include "dpu_core_irq.h" +#include "disp/msm_disp_snapshot.h" -#define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\ +#define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) -#define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\ +#define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\ (p) ? (p)->parent->base.id : -1, \ (p) ? (p)->intf_idx - INTF_0 : -1, \ (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ @@ -253,7 +254,7 @@ void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, } static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, - int32_t hw_id, struct dpu_encoder_wait_info *info); + u32 irq_idx, struct dpu_encoder_wait_info *info); int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, enum dpu_intr_idx intr_idx, @@ -273,27 +274,27 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, /* return EWOULDBLOCK since we know the wait isn't necessary */ if (phys_enc->enable_state == DPU_ENC_DISABLED) { - DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d", + DRMID(phys_enc->parent), intr_idx, irq->irq_idx); return -EWOULDBLOCK; } if (irq->irq_idx < 0) { - DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s", + DRMID(phys_enc->parent), intr_idx, irq->name); return 0; } - DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d", + DRMID(phys_enc->parent), intr_idx, irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(wait_info->atomic_cnt)); ret = dpu_encoder_helper_wait_event_timeout( DRMID(phys_enc->parent), - irq->hw_idx, + irq->irq_idx, wait_info); if (ret <= 0) { @@ -303,9 +304,9 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, unsigned long flags; DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, " - "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", + "irq=%d, pp=%d, atomic_cnt=%d", DRMID(phys_enc->parent), intr_idx, - irq->hw_idx, irq->irq_idx, + irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(wait_info->atomic_cnt)); local_irq_save(flags); @@ -315,16 +316,16 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, } else { ret = -ETIMEDOUT; DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, " - "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", + "irq=%d, pp=%d, atomic_cnt=%d", DRMID(phys_enc->parent), intr_idx, - irq->hw_idx, irq->irq_idx, + irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(wait_info->atomic_cnt)); } } else { ret = 0; trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), - intr_idx, irq->hw_idx, irq->irq_idx, + intr_idx, irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(wait_info->atomic_cnt)); } @@ -344,19 +345,9 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, } irq = &phys_enc->irq[intr_idx]; - if (irq->irq_idx >= 0) { - DPU_DEBUG_PHYS(phys_enc, - "skipping already registered irq %s type %d\n", - irq->name, irq->intr_type); - return 0; - } - - irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms, - irq->intr_type, irq->hw_idx); if (irq->irq_idx < 0) { DPU_ERROR_PHYS(phys_enc, - "failed to lookup IRQ index for %s type:%d\n", - irq->name, irq->intr_type); + "invalid IRQ index:%d\n", irq->irq_idx); return -EINVAL; } @@ -370,19 +361,8 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, return ret; } - ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1); - if (ret) { - DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, - irq->irq_idx); - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - irq->irq_idx, &irq->cb); - irq->irq_idx = -EINVAL; - return ret; - } - trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, - irq->hw_idx, irq->irq_idx); + irq->irq_idx); return ret; } @@ -397,31 +377,22 @@ int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, /* silently skip irqs that weren't registered */ if (irq->irq_idx < 0) { - DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d", + DRMID(phys_enc->parent), intr_idx, irq->irq_idx); return 0; } - ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1); - if (ret) { - DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, - irq->irq_idx, ret); - } - ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, &irq->cb); if (ret) { - DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d", + DRMID(phys_enc->parent), intr_idx, irq->irq_idx, ret); } trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, - irq->hw_idx, irq->irq_idx); - - irq->irq_idx = -EINVAL; + irq->irq_idx); return 0; } @@ -820,13 +791,13 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, /* return if the resource control is already in ON state */ if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { - DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n", + DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", DRMID(drm_enc), sw_event); mutex_unlock(&dpu_enc->rc_lock); return 0; } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { - DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n", + DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", DRMID(drm_enc), sw_event, dpu_enc->rc_state); mutex_unlock(&dpu_enc->rc_lock); @@ -1336,6 +1307,11 @@ static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, DPU_ATRACE_BEGIN("encoder_underrun_callback"); atomic_inc(&phy_enc->underrun_cnt); + + /* trigger dump only on the first underrun */ + if (atomic_read(&phy_enc->underrun_cnt) == 1) + msm_disp_snapshot_state(drm_enc->dev); + trace_dpu_enc_underrun_cb(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt)); DPU_ATRACE_END("encoder_underrun_callback"); @@ -1453,11 +1429,6 @@ static void dpu_encoder_off_work(struct work_struct *work) struct dpu_encoder_virt *dpu_enc = container_of(work, struct dpu_encoder_virt, delayed_off_work.work); - if (!dpu_enc) { - DPU_ERROR("invalid dpu encoder\n"); - return; - } - dpu_encoder_resource_control(&dpu_enc->base, DPU_ENC_RC_EVENT_ENTER_IDLE); @@ -1537,7 +1508,7 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) static int dpu_encoder_helper_wait_event_timeout( int32_t drm_id, - int32_t hw_id, + u32 irq_idx, struct dpu_encoder_wait_info *info) { int rc = 0; @@ -1550,7 +1521,7 @@ static int dpu_encoder_helper_wait_event_timeout( atomic_read(info->atomic_cnt) == 0, jiffies); time = ktime_to_ms(ktime_get()); - trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time, + trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time, expected_time, atomic_read(info->atomic_cnt)); /* If we timed out, counter is valid and time is less, wait again */ @@ -1565,19 +1536,23 @@ static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) struct dpu_encoder_virt *dpu_enc; struct dpu_hw_ctl *ctl; int rc; + struct drm_encoder *drm_enc; dpu_enc = to_dpu_encoder_virt(phys_enc->parent); ctl = phys_enc->hw_ctl; + drm_enc = phys_enc->parent; if (!ctl->ops.reset) return; - DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), + DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), ctl->idx); rc = ctl->ops.reset(ctl); - if (rc) + if (rc) { DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); + msm_disp_snapshot_state(drm_enc->dev); + } phys_enc->enable_state = DPU_ENC_ENABLED; } @@ -1797,11 +1772,6 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) struct dpu_encoder_virt, vsync_event_work); ktime_t wakeup_time; - if (!dpu_enc) { - DPU_ERROR("invalid dpu encoder\n"); - return; - } - if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) return; @@ -2068,8 +2038,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, phys_params.parent_ops = &dpu_encoder_parent_ops; phys_params.enc_spinlock = &dpu_enc->enc_spinlock; - DPU_DEBUG("\n"); - switch (disp_info->intf_type) { case DRM_MODE_ENCODER_DSI: intf_type = INTF_DSI; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index ecbc4be98980..e7270eb6b84b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -165,18 +165,14 @@ enum dpu_intr_idx { /** * dpu_encoder_irq - tracking structure for interrupts * @name: string name of interrupt - * @intr_type: Encoder interrupt type * @intr_idx: Encoder interrupt enumeration - * @hw_idx: HW Block ID * @irq_idx: IRQ interface lookup index from DPU IRQ framework * will be -EINVAL if IRQ is not registered * @irq_cb: interrupt callback */ struct dpu_encoder_irq { const char *name; - enum dpu_intr_type intr_type; enum dpu_intr_idx intr_idx; - int hw_idx; int irq_idx; struct dpu_irq_callback cb; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b2be39b9144e..aa01698d6b25 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ @@ -11,6 +11,7 @@ #include "dpu_core_irq.h" #include "dpu_formats.h" #include "dpu_trace.h" +#include "disp/msm_disp_snapshot.h" #define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ (e) && (e)->base.parent ? \ @@ -143,28 +144,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx) phys_enc); } -static void _dpu_encoder_phys_cmd_setup_irq_hw_idx( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_encoder_irq *irq; - - irq = &phys_enc->irq[INTR_IDX_CTL_START]; - irq->hw_idx = phys_enc->hw_ctl->idx; - irq->irq_idx = -EINVAL; - - irq = &phys_enc->irq[INTR_IDX_PINGPONG]; - irq->hw_idx = phys_enc->hw_pp->idx; - irq->irq_idx = -EINVAL; - - irq = &phys_enc->irq[INTR_IDX_RDPTR]; - irq->hw_idx = phys_enc->hw_pp->idx; - irq->irq_idx = -EINVAL; - - irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; - irq->hw_idx = phys_enc->intf_idx; - irq->irq_idx = -EINVAL; -} - static void dpu_encoder_phys_cmd_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_display_mode *mode, @@ -172,6 +151,7 @@ static void dpu_encoder_phys_cmd_mode_set( { struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); + struct dpu_encoder_irq *irq; if (!mode || !adj_mode) { DPU_ERROR("invalid args\n"); @@ -181,7 +161,17 @@ static void dpu_encoder_phys_cmd_mode_set( DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n"); drm_mode_debug_printmodeline(adj_mode); - _dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc); + irq = &phys_enc->irq[INTR_IDX_CTL_START]; + irq->irq_idx = phys_enc->hw_ctl->caps->intr_start; + + irq = &phys_enc->irq[INTR_IDX_PINGPONG]; + irq->irq_idx = phys_enc->hw_pp->caps->intr_done; + + irq = &phys_enc->irq[INTR_IDX_RDPTR]; + irq->irq_idx = phys_enc->hw_pp->caps->intr_rdptr; + + irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; + irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun; } static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( @@ -191,10 +181,13 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( to_dpu_encoder_phys_cmd(phys_enc); u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR; bool do_log = false; + struct drm_encoder *drm_enc; if (!phys_enc->hw_pp) return -EINVAL; + drm_enc = phys_enc->parent; + cmd_enc->pp_timeout_report_cnt++; if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) { frame_event |= DPU_ENCODER_FRAME_EVENT_PANEL_DEAD; @@ -203,7 +196,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( do_log = true; } - trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent), + trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(drm_enc), phys_enc->hw_pp->idx - PINGPONG_0, cmd_enc->pp_timeout_report_cnt, atomic_read(&phys_enc->pending_kickoff_cnt), @@ -212,12 +205,12 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( /* to avoid flooding, only log first time, and "dead" time */ if (do_log) { DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n", - DRMID(phys_enc->parent), + DRMID(drm_enc), phys_enc->hw_pp->idx - PINGPONG_0, phys_enc->hw_ctl->idx - CTL_0, cmd_enc->pp_timeout_report_cnt, atomic_read(&phys_enc->pending_kickoff_cnt)); - + msm_disp_snapshot_state(drm_enc->dev); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR); } @@ -228,7 +221,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( if (phys_enc->parent_ops->handle_frame_done) phys_enc->parent_ops->handle_frame_done( - phys_enc->parent, phys_enc, frame_event); + drm_enc, phys_enc, frame_event); return -ETIMEDOUT; } @@ -685,10 +678,6 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete( static int dpu_encoder_phys_cmd_wait_for_commit_done( struct dpu_encoder_phys *phys_enc) { - struct dpu_encoder_phys_cmd *cmd_enc; - - cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - /* only required for master controller */ if (!dpu_encoder_phys_cmd_is_master(phys_enc)) return 0; @@ -795,31 +784,26 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( irq = &phys_enc->irq[i]; INIT_LIST_HEAD(&irq->cb.list); irq->irq_idx = -EINVAL; - irq->hw_idx = -EINVAL; irq->cb.arg = phys_enc; } irq = &phys_enc->irq[INTR_IDX_CTL_START]; irq->name = "ctl_start"; - irq->intr_type = DPU_IRQ_TYPE_CTL_START; irq->intr_idx = INTR_IDX_CTL_START; irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq; irq = &phys_enc->irq[INTR_IDX_PINGPONG]; irq->name = "pp_done"; - irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP; irq->intr_idx = INTR_IDX_PINGPONG; irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq; irq = &phys_enc->irq[INTR_IDX_RDPTR]; irq->name = "pp_rd_ptr"; - irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR; irq->intr_idx = INTR_IDX_RDPTR; irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq; irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; irq->name = "underrun"; - irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN; irq->intr_idx = INTR_IDX_UNDERRUN; irq->cb.func = dpu_encoder_phys_cmd_underrun_irq; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 0e06b7e73c7a..185379b18572 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ @@ -9,6 +9,7 @@ #include "dpu_core_irq.h" #include "dpu_formats.h" #include "dpu_trace.h" +#include "disp/msm_disp_snapshot.h" #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ (e) && (e)->parent ? \ @@ -284,7 +285,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( intf_cfg.stream_sel = 0; /* Don't care value for video mode */ intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); if (phys_enc->hw_pp->merge_3d) - intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id; + intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, @@ -298,11 +299,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( true, phys_enc->hw_pp->idx); - if (phys_enc->hw_pp->merge_3d) { - struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d); - - merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d); - } + if (phys_enc->hw_pp->merge_3d) + phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -363,38 +361,24 @@ static bool dpu_encoder_phys_vid_needs_single_flush( return phys_enc->split_role != ENC_ROLE_SOLO; } -static void _dpu_encoder_phys_vid_setup_irq_hw_idx( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_encoder_irq *irq; - - /* - * Initialize irq->hw_idx only when irq is not registered. - * Prevent invalidating irq->irq_idx as modeset may be - * called many times during dfps. - */ - - irq = &phys_enc->irq[INTR_IDX_VSYNC]; - if (irq->irq_idx < 0) - irq->hw_idx = phys_enc->intf_idx; - - irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; - if (irq->irq_idx < 0) - irq->hw_idx = phys_enc->intf_idx; -} - static void dpu_encoder_phys_vid_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { + struct dpu_encoder_irq *irq; + if (adj_mode) { phys_enc->cached_mode = *adj_mode; drm_mode_debug_printmodeline(adj_mode); DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n"); } - _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc); + irq = &phys_enc->irq[INTR_IDX_VSYNC]; + irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync; + + irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; + irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun; } static int dpu_encoder_phys_vid_control_vblank_irq( @@ -416,7 +400,7 @@ static int dpu_encoder_phys_vid_control_vblank_irq( goto end; } - DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, + DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, atomic_read(&phys_enc->vblank_refcount)); if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) @@ -461,13 +445,14 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) - ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id); + ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); skip_flush: DPU_DEBUG_VIDENC(phys_enc, "update pending flush ctl %d intf %d\n", ctl->idx - CTL_0, phys_enc->hw_intf->idx); + atomic_set(&phys_enc->underrun_cnt, 0); /* ctl_flush & timing engine enable will be triggered by framework */ if (phys_enc->enable_state == DPU_ENC_DISABLED) @@ -537,6 +522,9 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( { struct dpu_hw_ctl *ctl; int rc; + struct drm_encoder *drm_enc; + + drm_enc = phys_enc->parent; ctl = phys_enc->hw_ctl; if (!ctl->ops.wait_reset_status) @@ -550,6 +538,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( if (rc) { DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n", ctl->idx, rc); + msm_disp_snapshot_state(drm_enc->dev); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC); } } @@ -636,7 +625,7 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, if (enable) { ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); - if (ret) + if (WARN_ON(ret)) return; dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN); @@ -738,19 +727,16 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( irq = &phys_enc->irq[i]; INIT_LIST_HEAD(&irq->cb.list); irq->irq_idx = -EINVAL; - irq->hw_idx = -EINVAL; irq->cb.arg = phys_enc; } irq = &phys_enc->irq[INTR_IDX_VSYNC]; irq->name = "vsync_irq"; - irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC; irq->intr_idx = INTR_IDX_VSYNC; irq->cb.func = dpu_encoder_phys_vid_vblank_irq; irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; irq->name = "underrun"; - irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN; irq->intr_idx = INTR_IDX_UNDERRUN; irq->cb.func = dpu_encoder_phys_vid_underrun_irq; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 21ff8f9e5dfd..440ae93d7bd1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -992,7 +992,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( * Currently only support exactly zero or one modifier. * All planes use the same modifier. */ - DPU_DEBUG("plane format modifier 0x%llX\n", modifier); + DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier); switch (modifier) { case 0: @@ -1002,7 +1002,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( case DRM_FORMAT_MOD_QCOM_COMPRESSED: map = dpu_format_map_ubwc; map_size = ARRAY_SIZE(dpu_format_map_ubwc); - DPU_DEBUG("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n", + DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n", (char *)&format); break; default: @@ -1021,7 +1021,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n", (char *)&format, modifier); else - DPU_DEBUG("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n", + DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n", (char *)&format, modifier, DPU_FORMAT_IS_UBWC(fmt), DPU_FORMAT_IS_YUV(fmt)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c deleted file mode 100644 index 819b26e660b9..000000000000 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - */ - -#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ - -#include <linux/mutex.h> -#include <linux/errno.h> -#include <linux/slab.h> - -#include "dpu_hw_mdss.h" -#include "dpu_hw_blk.h" - -/* Serialization lock for dpu_hw_blk_list */ -static DEFINE_MUTEX(dpu_hw_blk_lock); - -/* List of all hw block objects */ -static LIST_HEAD(dpu_hw_blk_list); - -/** - * dpu_hw_blk_init - initialize hw block object - * @hw_blk: pointer to hw block object - * @type: hw block type - enum dpu_hw_blk_type - * @id: instance id of the hw block - * @ops: Pointer to block operations - */ -void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, - struct dpu_hw_blk_ops *ops) -{ - INIT_LIST_HEAD(&hw_blk->list); - hw_blk->type = type; - hw_blk->id = id; - atomic_set(&hw_blk->refcount, 0); - - if (ops) - hw_blk->ops = *ops; - - mutex_lock(&dpu_hw_blk_lock); - list_add(&hw_blk->list, &dpu_hw_blk_list); - mutex_unlock(&dpu_hw_blk_lock); -} - -/** - * dpu_hw_blk_destroy - destroy hw block object. - * @hw_blk: pointer to hw block object - * return: none - */ -void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk) -{ - if (!hw_blk) { - pr_err("invalid parameters\n"); - return; - } - - if (atomic_read(&hw_blk->refcount)) - pr_err("hw_blk:%d.%d invalid refcount\n", hw_blk->type, - hw_blk->id); - - mutex_lock(&dpu_hw_blk_lock); - list_del(&hw_blk->list); - mutex_unlock(&dpu_hw_blk_lock); -} - -/** - * dpu_hw_blk_get - get hw_blk from free pool - * @hw_blk: if specified, increment reference count only - * @type: if hw_blk is not specified, allocate the next available of this type - * @id: if specified (>= 0), allocate the given instance of the above type - * return: pointer to hw block object - */ -struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id) -{ - struct dpu_hw_blk *curr; - int rc, refcount; - - if (!hw_blk) { - mutex_lock(&dpu_hw_blk_lock); - list_for_each_entry(curr, &dpu_hw_blk_list, list) { - if ((curr->type != type) || - (id >= 0 && curr->id != id) || - (id < 0 && - atomic_read(&curr->refcount))) - continue; - - hw_blk = curr; - break; - } - mutex_unlock(&dpu_hw_blk_lock); - } - - if (!hw_blk) { - pr_debug("no hw_blk:%d\n", type); - return NULL; - } - - refcount = atomic_inc_return(&hw_blk->refcount); - - if (refcount == 1 && hw_blk->ops.start) { - rc = hw_blk->ops.start(hw_blk); - if (rc) { - pr_err("failed to start hw_blk:%d rc:%d\n", type, rc); - goto error_start; - } - } - - pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, - hw_blk->id, refcount); - return hw_blk; - -error_start: - dpu_hw_blk_put(hw_blk); - return ERR_PTR(rc); -} - -/** - * dpu_hw_blk_put - put hw_blk to free pool if decremented refcount is zero - * @hw_blk: hw block to be freed - */ -void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk) -{ - if (!hw_blk) { - pr_err("invalid parameters\n"); - return; - } - - pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, hw_blk->id, - atomic_read(&hw_blk->refcount)); - - if (!atomic_read(&hw_blk->refcount)) { - pr_err("hw_blk:%d.%d invalid put\n", hw_blk->type, hw_blk->id); - return; - } - - if (atomic_dec_return(&hw_blk->refcount)) - return; - - if (hw_blk->ops.stop) - hw_blk->ops.stop(hw_blk); -} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h index 2bf737f8dd1b..52e92f37eda4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h @@ -7,19 +7,9 @@ #include <linux/types.h> #include <linux/list.h> -#include <linux/atomic.h> struct dpu_hw_blk; -/** - * struct dpu_hw_blk_ops - common hardware block operations - * @start: start operation on first get - * @stop: stop operation on last put - */ -struct dpu_hw_blk_ops { - int (*start)(struct dpu_hw_blk *); - void (*stop)(struct dpu_hw_blk *); -}; /** * struct dpu_hw_blk - definition of hardware block object @@ -29,17 +19,7 @@ struct dpu_hw_blk_ops { * @refcount: reference/usage count */ struct dpu_hw_blk { - struct list_head list; - u32 type; - int id; - atomic_t refcount; - struct dpu_hw_blk_ops ops; + /* opaque */ }; -void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, - struct dpu_hw_blk_ops *ops); -void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk); - -struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id); -void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk); #endif /*_DPU_HW_BLK_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b569030a0847..d01c4c919504 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -7,6 +7,7 @@ #include <linux/of_address.h> #include <linux/platform_device.h> #include "dpu_hw_mdss.h" +#include "dpu_hw_interrupts.h" #include "dpu_hw_catalog.h" #include "dpu_kms.h" @@ -56,12 +57,39 @@ #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) -#define INTR_SC7180_MASK \ - (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\ - BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\ - BIT(DPU_IRQ_TYPE_PING_PONG_AUTO_REF) |\ - BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\ - BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK)) +#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR) | \ + BIT(MDP_AD4_0_INTR) | \ + BIT(MDP_AD4_1_INTR)) + +#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR)) + +#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF5_7xxx_INTR)) + +#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR)) + #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) #define DEFAULT_DPU_LINE_WIDTH 2048 @@ -315,27 +343,32 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0xE4, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0xE4, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0xE4, - .features = 0 + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0xE4, - .features = 0 + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0xE4, - .features = 0 + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; @@ -343,17 +376,20 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0xE4, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0xE4, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0xE4, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, }; @@ -361,32 +397,38 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name = "ctl_5", .id = CTL_5, .base = 0x1a00, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; @@ -394,22 +436,26 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x15000, .len = 0x1E8, - .features = CTL_SC7280_MASK + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x16000, .len = 0x1E8, - .features = CTL_SC7280_MASK + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x17000, .len = 0x1E8, - .features = CTL_SC7280_MASK + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x18000, .len = 0x1E8, - .features = CTL_SC7280_MASK + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, }; @@ -690,42 +736,66 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { .len = 0x20, .version = 0x20000}, }; -#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \ +#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0xd4, \ .features = PINGPONG_SDM845_SPLIT_MASK, \ .merge_3d = _merge_3d, \ - .sblk = &_sblk \ + .sblk = &_sblk, \ + .intr_done = _done, \ + .intr_rdptr = _rdptr, \ } -#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \ +#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0xd4, \ .features = PINGPONG_SDM845_MASK, \ .merge_3d = _merge_3d, \ - .sblk = &_sblk \ + .sblk = &_sblk, \ + .intr_done = _done, \ + .intr_rdptr = _rdptr, \ } static const struct dpu_pingpong_cfg sdm845_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), }; static struct dpu_pingpong_cfg sc7180_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), }; static const struct dpu_pingpong_cfg sm8150_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk), - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk), - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), }; /************************************************************* @@ -746,47 +816,49 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { }; static const struct dpu_pingpong_cfg sc7280_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk), - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk), - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk), - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk), + PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), }; /************************************************************* * INTF sub blocks config *************************************************************/ -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features) \ +#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0x280, \ .features = _features, \ .type = _type, \ .controller_id = _ctrl_id, \ - .prog_fetch_lines_worst_case = _progfetch \ + .prog_fetch_lines_worst_case = _progfetch, \ + .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \ + .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ } static const struct dpu_intf_cfg sdm845_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), }; static const struct dpu_intf_cfg sc7180_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), }; static const struct dpu_intf_cfg sm8150_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), }; static const struct dpu_intf_cfg sc7280_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK), - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK), - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK), + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), }; /************************************************************* @@ -1060,7 +1132,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .reg_dma_count = 1, .dma_cfg = sdm845_regdma, .perf = sdm845_perf_data, - .mdss_irqs = 0x3ff, + .mdss_irqs = IRQ_SDM845_MASK, }; } @@ -1091,8 +1163,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .reg_dma_count = 1, .dma_cfg = sdm845_regdma, .perf = sc7180_perf_data, - .mdss_irqs = 0x3f, - .obsolete_irq = INTR_SC7180_MASK, + .mdss_irqs = IRQ_SC7180_MASK, }; } @@ -1125,7 +1196,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .reg_dma_count = 1, .dma_cfg = sm8150_regdma, .perf = sm8150_perf_data, - .mdss_irqs = 0x3ff, + .mdss_irqs = IRQ_SDM845_MASK, }; } @@ -1158,7 +1229,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .reg_dma_count = 1, .dma_cfg = sm8250_regdma, .perf = sm8250_perf_data, - .mdss_irqs = 0xff, + .mdss_irqs = IRQ_SM8250_MASK, }; } @@ -1181,8 +1252,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = sc7280_perf_data, - .mdss_irqs = 0x1c07, - .obsolete_irq = INTR_SC7180_MASK, + .mdss_irqs = IRQ_SC7280_MASK, }; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4dfd8a20ad5c..d2a945a27cfa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. */ #ifndef _DPU_HW_CATALOG_H @@ -464,13 +464,15 @@ struct dpu_mdp_cfg { struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; }; -/* struct dpu_mdp_cfg : MDP TOP-BLK instance info +/* struct dpu_ctl_cfg : MDP CTL instance info * @id: index identifying this block * @base: register base offset to mdss * @features bit mask identifying sub-blocks/features + * @intr_start: interrupt index for CTL_START */ struct dpu_ctl_cfg { DPU_HW_BLK_INFO; + s32 intr_start; }; /** @@ -526,11 +528,15 @@ struct dpu_dspp_cfg { * @id enum identifying this block * @base register offset of this block * @features bit mask identifying sub-blocks/features + * @intr_done: index for PINGPONG done interrupt + * @intr_rdptr: index for PINGPONG readpointer done interrupt * @sblk sub-blocks information */ struct dpu_pingpong_cfg { DPU_HW_BLK_INFO; u32 merge_3d; + s32 intr_done; + s32 intr_rdptr; const struct dpu_pingpong_sub_blks *sblk; }; @@ -555,12 +561,16 @@ struct dpu_merge_3d_cfg { * @type: Interface type(DSI, DP, HDMI) * @controller_id: Controller Instance ID in case of multiple of intf type * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch + * @intr_underrun: index for INTF underrun interrupt + * @intr_vsync: index for INTF VSYNC interrupt */ struct dpu_intf_cfg { DPU_HW_BLK_INFO; u32 type; /* interface type*/ u32 controller_id; u32 prog_fetch_lines_worst_case; + s32 intr_underrun; + s32 intr_vsync; }; /** @@ -723,7 +733,6 @@ struct dpu_perf_cfg { * @cursor_formats Supported formats for cursor pipe * @vig_formats Supported formats for vig pipe * @mdss_irqs: Bitmap with the irqs supported by the target - * @obsolete_irq: Irq types that are obsolete for a particular target */ struct dpu_mdss_cfg { u32 hwversion; @@ -770,7 +779,6 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; unsigned long mdss_irqs; - unsigned long obsolete_irq; }; struct dpu_mdss_hw_cfg_handler { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 2d4645e01ebf..f8a74f6cdc4c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -589,8 +589,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -615,14 +613,10 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, c->mixer_count = m->mixer_count; c->mixer_hw_caps = m->mixer; - dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops); - return c; } void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx) { - if (ctx) - dpu_hw_blk_destroy(&ctx->base); kfree(ctx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index e42f901a7de5..a98e964c3b6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -85,8 +85,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, return ERR_PTR(-EINVAL); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -112,16 +110,11 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, c->cap = cfg; _setup_dspp_ops(c, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops); - return c; } void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp) { - if (dspp) - dpu_hw_blk_destroy(&dspp->base); - kfree(dspp); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 48c96b812126..2e816f232e85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -30,145 +30,6 @@ #define MDP_INTF_5_OFF_REV_7xxx 0x39000 /** - * WB interrupt status bit definitions - */ -#define DPU_INTR_WB_0_DONE BIT(0) -#define DPU_INTR_WB_1_DONE BIT(1) -#define DPU_INTR_WB_2_DONE BIT(4) - -/** - * WDOG timer interrupt status bit definitions - */ -#define DPU_INTR_WD_TIMER_0_DONE BIT(2) -#define DPU_INTR_WD_TIMER_1_DONE BIT(3) -#define DPU_INTR_WD_TIMER_2_DONE BIT(5) -#define DPU_INTR_WD_TIMER_3_DONE BIT(6) -#define DPU_INTR_WD_TIMER_4_DONE BIT(7) - -/** - * Pingpong interrupt status bit definitions - */ -#define DPU_INTR_PING_PONG_0_DONE BIT(8) -#define DPU_INTR_PING_PONG_1_DONE BIT(9) -#define DPU_INTR_PING_PONG_2_DONE BIT(10) -#define DPU_INTR_PING_PONG_3_DONE BIT(11) -#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12) -#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13) -#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14) -#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15) -#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16) -#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17) -#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18) -#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19) -#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20) -#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21) -#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22) -#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23) - -/** - * Interface interrupt status bit definitions - */ -#define DPU_INTR_INTF_0_UNDERRUN BIT(24) -#define DPU_INTR_INTF_1_UNDERRUN BIT(26) -#define DPU_INTR_INTF_2_UNDERRUN BIT(28) -#define DPU_INTR_INTF_3_UNDERRUN BIT(30) -#define DPU_INTR_INTF_5_UNDERRUN BIT(22) -#define DPU_INTR_INTF_0_VSYNC BIT(25) -#define DPU_INTR_INTF_1_VSYNC BIT(27) -#define DPU_INTR_INTF_2_VSYNC BIT(29) -#define DPU_INTR_INTF_3_VSYNC BIT(31) -#define DPU_INTR_INTF_5_VSYNC BIT(23) - -/** - * Pingpong Secondary interrupt status bit definitions - */ -#define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0) -#define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4) -#define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8) -#define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22) -#define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28) - -/** - * Pingpong TEAR detection interrupt status bit definitions - */ -#define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16) -#define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17) -#define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18) -#define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19) - -/** - * Pingpong TE detection interrupt status bit definitions - */ -#define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24) -#define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25) -#define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26) -#define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27) - -/** - * Ctl start interrupt status bit definitions - */ -#define DPU_INTR_CTL_0_START BIT(9) -#define DPU_INTR_CTL_1_START BIT(10) -#define DPU_INTR_CTL_2_START BIT(11) -#define DPU_INTR_CTL_3_START BIT(12) -#define DPU_INTR_CTL_4_START BIT(13) - -/** - * Concurrent WB overflow interrupt status bit definitions - */ -#define DPU_INTR_CWB_2_OVERFLOW BIT(14) -#define DPU_INTR_CWB_3_OVERFLOW BIT(15) - -/** - * Histogram VIG done interrupt status bit definitions - */ -#define DPU_INTR_HIST_VIG_0_DONE BIT(0) -#define DPU_INTR_HIST_VIG_1_DONE BIT(4) -#define DPU_INTR_HIST_VIG_2_DONE BIT(8) -#define DPU_INTR_HIST_VIG_3_DONE BIT(10) - -/** - * Histogram VIG reset Sequence done interrupt status bit definitions - */ -#define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1) -#define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5) -#define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9) -#define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11) - -/** - * Histogram DSPP done interrupt status bit definitions - */ -#define DPU_INTR_HIST_DSPP_0_DONE BIT(12) -#define DPU_INTR_HIST_DSPP_1_DONE BIT(16) -#define DPU_INTR_HIST_DSPP_2_DONE BIT(20) -#define DPU_INTR_HIST_DSPP_3_DONE BIT(22) - -/** - * Histogram DSPP reset Sequence done interrupt status bit definitions - */ -#define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13) -#define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17) -#define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21) -#define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23) - -/** - * INTF interrupt status bit definitions - */ -#define DPU_INTR_VIDEO_INTO_STATIC BIT(0) -#define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1) -#define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2) -#define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3) -#define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4) -#define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5) -#define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6) -#define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7) -#define DPU_INTR_PROG_LINE BIT(8) - -/** - * AD4 interrupt status bit definitions - */ -#define DPU_INTR_BACKLIGHT_UPDATED BIT(0) -/** * struct dpu_intr_reg - array of DPU register sets * @clr_off: offset to CLEAR reg * @en_off: offset to ENABLE reg @@ -180,22 +41,10 @@ struct dpu_intr_reg { u32 status_off; }; -/** - * struct dpu_irq_type - maps each irq with i/f - * @intr_type: type of interrupt listed in dpu_intr_type - * @instance_idx: instance index of the associated HW block in DPU - * @irq_mask: corresponding bit in the interrupt status reg - * @reg_idx: which reg set to use - */ -struct dpu_irq_type { - u32 intr_type; - u32 instance_idx; - u32 irq_mask; - u32 reg_idx; -}; - /* * struct dpu_intr_reg - List of DPU interrupt registers + * + * When making changes be sure to sync with dpu_hw_intr_reg */ static const struct dpu_intr_reg dpu_intr_set[] = { { @@ -265,1101 +114,22 @@ static const struct dpu_intr_reg dpu_intr_set[] = { }, }; -/* - * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this - * table that have a matching interface type and - * instance index. - */ -static const struct dpu_irq_type dpu_irq_map[] = { - /* BEGIN MAP_RANGE: 0-31, INTR */ - /* irq_idx: 0-3 */ - { DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0}, - { DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0}, - /* irq_idx: 4-7 */ - { DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0}, - /* irq_idx: 8-11 */ - { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0, - DPU_INTR_PING_PONG_0_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1, - DPU_INTR_PING_PONG_1_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2, - DPU_INTR_PING_PONG_2_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3, - DPU_INTR_PING_PONG_3_DONE, 0}, - /* irq_idx: 12-15 */ - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0, - DPU_INTR_PING_PONG_0_RD_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1, - DPU_INTR_PING_PONG_1_RD_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2, - DPU_INTR_PING_PONG_2_RD_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3, - DPU_INTR_PING_PONG_3_RD_PTR, 0}, - /* irq_idx: 16-19 */ - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0, - DPU_INTR_PING_PONG_0_WR_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1, - DPU_INTR_PING_PONG_1_WR_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2, - DPU_INTR_PING_PONG_2_WR_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3, - DPU_INTR_PING_PONG_3_WR_PTR, 0}, - /* irq_idx: 20-23 */ - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0, - DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1, - DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2, - DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3, - DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0}, - /* irq_idx: 24-27 */ - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0}, - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0}, - /* irq_idx: 28-31 */ - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0}, - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0}, - /* irq_idx:32-33 */ - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0}, - /* irq_idx:34-63 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - /* BEGIN MAP_RANGE: 64-95, INTR2 */ - /* irq_idx: 64-67 */ - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 68-71 */ - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_WR_PTR, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 72 */ - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_RD_PTR, 1}, - /* irq_idx: 73-77 */ - { DPU_IRQ_TYPE_CTL_START, CTL_0, - DPU_INTR_CTL_0_START, 1}, - { DPU_IRQ_TYPE_CTL_START, CTL_1, - DPU_INTR_CTL_1_START, 1}, - { DPU_IRQ_TYPE_CTL_START, CTL_2, - DPU_INTR_CTL_2_START, 1}, - { DPU_IRQ_TYPE_CTL_START, CTL_3, - DPU_INTR_CTL_3_START, 1}, - { DPU_IRQ_TYPE_CTL_START, CTL_4, - DPU_INTR_CTL_4_START, 1}, - /* irq_idx: 78-79 */ - { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1}, - { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1}, - /* irq_idx: 80-83 */ - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0, - DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1, - DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2, - DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3, - DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1}, - /* irq_idx: 84-87 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 88-91 */ - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0, - DPU_INTR_PING_PONG_0_TE_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1, - DPU_INTR_PING_PONG_1_TE_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2, - DPU_INTR_PING_PONG_2_TE_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3, - DPU_INTR_PING_PONG_3_TE_DETECTED, 1}, - /* irq_idx: 92-95 */ - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_TE_DETECTED, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 96-127 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* BEGIN MAP_RANGE: 128-159 HIST */ - /* irq_idx: 128-131 */ - { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0, - DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 132-135 */ - { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1, - DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 136-139 */ - { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2, - DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3, - DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2}, - /* irq_idx: 140-143 */ - { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0, - DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 144-147 */ - { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1, - DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 148-151 */ - { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2, - DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3, - DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2}, - /* irq_idx: 152-155 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 156-159 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 160-191 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */ - /* irq_idx: 192-195 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, - DPU_INTR_VIDEO_INTO_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, - DPU_INTR_VIDEO_OUTOF_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0, - DPU_INTR_DSICMD_0_INTO_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 3}, - /* irq_idx: 196-199 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, - DPU_INTR_DSICMD_1_INTO_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0, - DPU_INTR_DSICMD_2_INTO_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 3}, - /* irq_idx: 200-203 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 204-207 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 208-211 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 212-215 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 216-219 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 220-223 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 224-255 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */ - /* irq_idx: 256-259 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, - DPU_INTR_VIDEO_INTO_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, - DPU_INTR_VIDEO_OUTOF_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1, - DPU_INTR_DSICMD_0_INTO_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 4}, - /* irq_idx: 260-263 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, - DPU_INTR_DSICMD_1_INTO_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1, - DPU_INTR_DSICMD_2_INTO_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 4}, - /* irq_idx: 264-267 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 268-271 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 272-275 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 276-279 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 280-283 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 284-287 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 288-319 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */ - /* irq_idx: 320-323 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2, - DPU_INTR_VIDEO_INTO_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2, - DPU_INTR_VIDEO_OUTOF_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2, - DPU_INTR_DSICMD_0_INTO_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 5}, - /* irq_idx: 324-327 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2, - DPU_INTR_DSICMD_1_INTO_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2, - DPU_INTR_DSICMD_2_INTO_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 5}, - /* irq_idx: 328-331 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 332-335 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 336-339 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 340-343 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 344-347 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 348-351 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 352-383 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */ - /* irq_idx: 384-387 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3, - DPU_INTR_VIDEO_INTO_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3, - DPU_INTR_VIDEO_OUTOF_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3, - DPU_INTR_DSICMD_0_INTO_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 6}, - /* irq_idx: 388-391 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3, - DPU_INTR_DSICMD_1_INTO_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3, - DPU_INTR_DSICMD_2_INTO_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 6}, - /* irq_idx: 392-395 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 396-399 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 400-403 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 404-407 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 408-411 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 412-415 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 416-447*/ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */ - /* irq_idx: 448-451 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4, - DPU_INTR_VIDEO_INTO_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4, - DPU_INTR_VIDEO_OUTOF_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4, - DPU_INTR_DSICMD_0_INTO_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 7}, - /* irq_idx: 452-455 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4, - DPU_INTR_DSICMD_1_INTO_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4, - DPU_INTR_DSICMD_2_INTO_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 7}, - /* irq_idx: 456-459 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 460-463 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 464-467 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 468-471 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 472-475 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 476-479 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 480-511 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */ - /* irq_idx: 512-515 */ - { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 516-519 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 520-523 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 524-527 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 528-531 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 532-535 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 536-539 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 540-543 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 544-575*/ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */ - /* irq_idx: 576-579 */ - { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 580-583 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 584-587 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 588-591 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 592-595 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 596-599 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 600-603 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 604-607 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 608-639 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */ - /* irq_idx: 640-643 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, - DPU_INTR_VIDEO_INTO_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, - DPU_INTR_VIDEO_OUTOF_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0, - DPU_INTR_DSICMD_0_INTO_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 10}, - /* irq_idx: 644-647 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, - DPU_INTR_DSICMD_1_INTO_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0, - DPU_INTR_DSICMD_2_INTO_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 10}, - /* irq_idx: 648-651 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 652-655 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 656-659 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 660-663 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 664-667 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 668-671 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 672-703 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */ - /* irq_idx: 704-707 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, - DPU_INTR_VIDEO_INTO_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, - DPU_INTR_VIDEO_OUTOF_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1, - DPU_INTR_DSICMD_0_INTO_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 11}, - /* irq_idx: 708-711 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, - DPU_INTR_DSICMD_1_INTO_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1, - DPU_INTR_DSICMD_2_INTO_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 11}, - /* irq_idx: 712-715 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 716-719 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 720-723 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 724-727 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 728-731 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 732-735 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 736-767 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */ - /* irq_idx: 768-771 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5, - DPU_INTR_VIDEO_INTO_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5, - DPU_INTR_VIDEO_OUTOF_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5, - DPU_INTR_DSICMD_0_INTO_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 12}, - /* irq_idx: 772-775 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5, - DPU_INTR_DSICMD_1_INTO_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5, - DPU_INTR_DSICMD_2_INTO_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 12}, - /* irq_idx: 776-779 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 780-783 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 784-787 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 788-791 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 792-795 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 796-799 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 800-831 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, -}; +#define DPU_IRQ_REG(irq_idx) (irq_idx / 32) +#define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32)) -static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr, - enum dpu_intr_type intr_type, u32 instance_idx) +static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, + int irq_idx) { - int i; + int reg_idx; - for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) { - if (intr_type == dpu_irq_map[i].intr_type && - instance_idx == dpu_irq_map[i].instance_idx && - !(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type))) - return i; - } + if (!intr) + return; - pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n", - intr_type, instance_idx); - return -EINVAL; + reg_idx = DPU_IRQ_REG(irq_idx); + DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx)); + + /* ensure register writes go through */ + wmb(); } static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, @@ -1368,9 +138,9 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, { int reg_idx; int irq_idx; - int start_idx; - int end_idx; u32 irq_status; + u32 enable_mask; + int bit; unsigned long irq_flags; if (!intr) @@ -1383,86 +153,92 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, */ spin_lock_irqsave(&intr->irq_lock, irq_flags); for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { - irq_status = intr->save_irq_status[reg_idx]; + if (!test_bit(reg_idx, &intr->irq_mask)) + continue; - /* - * Each Interrupt register has a range of 64 indexes, and - * that is static for dpu_irq_map. - */ - start_idx = reg_idx * 64; - end_idx = start_idx + 64; + /* Read interrupt status */ + irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off); + + /* Read enable mask */ + enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off); + + /* and clear the interrupt */ + if (irq_status) + DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, + irq_status); - if (!test_bit(reg_idx, &intr->irq_mask) || - start_idx >= ARRAY_SIZE(dpu_irq_map)) + /* Finally update IRQ status based on enable mask */ + irq_status &= enable_mask; + + if (!irq_status) continue; /* - * Search through matching intr status from irq map. - * start_idx and end_idx defined the search range in - * the dpu_irq_map. + * Search through matching intr status. */ - for (irq_idx = start_idx; - (irq_idx < end_idx) && irq_status; - irq_idx++) - if ((irq_status & dpu_irq_map[irq_idx].irq_mask) && - (dpu_irq_map[irq_idx].reg_idx == reg_idx) && - !(intr->obsolete_irq & - BIT(dpu_irq_map[irq_idx].intr_type))) { - /* - * Once a match on irq mask, perform a callback - * to the given cbfunc. cbfunc will take care - * the interrupt status clearing. If cbfunc is - * not provided, then the interrupt clearing - * is here. - */ - if (cbfunc) - cbfunc(arg, irq_idx); - else - intr->ops.clear_intr_status_nolock( - intr, irq_idx); - - /* - * When callback finish, clear the irq_status - * with the matching mask. Once irq_status - * is all cleared, the search can be stopped. - */ - irq_status &= ~dpu_irq_map[irq_idx].irq_mask; - } + while ((bit = ffs(irq_status)) != 0) { + irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1); + /* + * Once a match on irq mask, perform a callback + * to the given cbfunc. cbfunc will take care + * the interrupt status clearing. If cbfunc is + * not provided, then the interrupt clearing + * is here. + */ + if (cbfunc) + cbfunc(arg, irq_idx); + + dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx); + + /* + * When callback finish, clear the irq_status + * with the matching mask. Once irq_status + * is all cleared, the search can be stopped. + */ + irq_status &= ~BIT(bit - 1); + } } + + /* ensure register writes go through */ + wmb(); + spin_unlock_irqrestore(&intr->irq_lock, irq_flags); } -static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) +static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx) { int reg_idx; - unsigned long irq_flags; const struct dpu_intr_reg *reg; - const struct dpu_irq_type *irq; const char *dbgstr = NULL; uint32_t cache_irq_mask; if (!intr) return -EINVAL; - if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { + if (irq_idx < 0 || irq_idx >= intr->total_irqs) { pr_err("invalid IRQ index: [%d]\n", irq_idx); return -EINVAL; } - irq = &dpu_irq_map[irq_idx]; - reg_idx = irq->reg_idx; + /* + * The cache_irq_mask and hardware RMW operations needs to be done + * under irq_lock and it's the caller's responsibility to ensure that's + * held. + */ + assert_spin_locked(&intr->irq_lock); + + reg_idx = DPU_IRQ_REG(irq_idx); reg = &dpu_intr_set[reg_idx]; - spin_lock_irqsave(&intr->irq_lock, irq_flags); cache_irq_mask = intr->cache_irq_mask[reg_idx]; - if (cache_irq_mask & irq->irq_mask) { + if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) { dbgstr = "DPU IRQ already set:"; } else { dbgstr = "DPU IRQ enabled:"; - cache_irq_mask |= irq->irq_mask; + cache_irq_mask |= DPU_IRQ_MASK(irq_idx); /* Cleaning any pending interrupt */ - DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); + DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); /* Enabling interrupts with the new mask */ DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); @@ -1471,45 +247,49 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) intr->cache_irq_mask[reg_idx] = cache_irq_mask; } - spin_unlock_irqrestore(&intr->irq_lock, irq_flags); - pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr, - irq->irq_mask, cache_irq_mask); + pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr, + DPU_IRQ_MASK(irq_idx), cache_irq_mask); return 0; } -static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) +static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx) { int reg_idx; const struct dpu_intr_reg *reg; - const struct dpu_irq_type *irq; const char *dbgstr = NULL; uint32_t cache_irq_mask; if (!intr) return -EINVAL; - if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { + if (irq_idx < 0 || irq_idx >= intr->total_irqs) { pr_err("invalid IRQ index: [%d]\n", irq_idx); return -EINVAL; } - irq = &dpu_irq_map[irq_idx]; - reg_idx = irq->reg_idx; + /* + * The cache_irq_mask and hardware RMW operations needs to be done + * under irq_lock and it's the caller's responsibility to ensure that's + * held. + */ + assert_spin_locked(&intr->irq_lock); + + reg_idx = DPU_IRQ_REG(irq_idx); reg = &dpu_intr_set[reg_idx]; cache_irq_mask = intr->cache_irq_mask[reg_idx]; - if ((cache_irq_mask & irq->irq_mask) == 0) { + if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) { dbgstr = "DPU IRQ is already cleared:"; } else { dbgstr = "DPU IRQ mask disable:"; - cache_irq_mask &= ~irq->irq_mask; + cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx); /* Disable interrupts based on the new mask */ DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); /* Cleaning any pending interrupt */ - DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); + DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); /* ensure register write goes through */ wmb(); @@ -1517,27 +297,8 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) intr->cache_irq_mask[reg_idx] = cache_irq_mask; } - pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr, - irq->irq_mask, cache_irq_mask); - - return 0; -} - -static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx) -{ - unsigned long irq_flags; - - if (!intr) - return -EINVAL; - - if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { - pr_err("invalid IRQ index: [%d]\n", irq_idx); - return -EINVAL; - } - - spin_lock_irqsave(&intr->irq_lock, irq_flags); - dpu_hw_intr_disable_irq_nolock(intr, irq_idx); - spin_unlock_irqrestore(&intr->irq_lock, irq_flags); + pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr, + DPU_IRQ_MASK(irq_idx), cache_irq_mask); return 0; } @@ -1580,58 +341,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) return 0; } -static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) -{ - int i; - u32 enable_mask; - unsigned long irq_flags; - - if (!intr) - return; - - spin_lock_irqsave(&intr->irq_lock, irq_flags); - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { - if (!test_bit(i, &intr->irq_mask)) - continue; - - /* Read interrupt status */ - intr->save_irq_status[i] = DPU_REG_READ(&intr->hw, - dpu_intr_set[i].status_off); - - /* Read enable mask */ - enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off); - - /* and clear the interrupt */ - if (intr->save_irq_status[i]) - DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, - intr->save_irq_status[i]); - - /* Finally update IRQ status based on enable mask */ - intr->save_irq_status[i] &= enable_mask; - } - - /* ensure register writes go through */ - wmb(); - - spin_unlock_irqrestore(&intr->irq_lock, irq_flags); -} - -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, - int irq_idx) -{ - int reg_idx; - - if (!intr) - return; - - reg_idx = dpu_irq_map[irq_idx].reg_idx; - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, - dpu_irq_map[irq_idx].irq_mask); - - /* ensure register writes go through */ - wmb(); -} - static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, int irq_idx, bool clear) { @@ -1642,17 +351,17 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, if (!intr) return 0; - if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) { + if (irq_idx < 0 || irq_idx >= intr->total_irqs) { pr_err("invalid IRQ index: [%d]\n", irq_idx); return 0; } spin_lock_irqsave(&intr->irq_lock, irq_flags); - reg_idx = dpu_irq_map[irq_idx].reg_idx; + reg_idx = DPU_IRQ_REG(irq_idx); intr_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off) & - dpu_irq_map[irq_idx].irq_mask; + DPU_IRQ_MASK(irq_idx); if (intr_status && clear) DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, intr_status); @@ -1665,17 +374,30 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, return intr_status; } +static unsigned long dpu_hw_intr_lock(struct dpu_hw_intr *intr) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&intr->irq_lock, irq_flags); + + return irq_flags; +} + +static void dpu_hw_intr_unlock(struct dpu_hw_intr *intr, unsigned long irq_flags) +{ + spin_unlock_irqrestore(&intr->irq_lock, irq_flags); +} + static void __setup_intr_ops(struct dpu_hw_intr_ops *ops) { - ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup; - ops->enable_irq = dpu_hw_intr_enable_irq; - ops->disable_irq = dpu_hw_intr_disable_irq; + ops->enable_irq_locked = dpu_hw_intr_enable_irq_locked; + ops->disable_irq_locked = dpu_hw_intr_disable_irq_locked; ops->dispatch_irqs = dpu_hw_intr_dispatch_irq; ops->clear_all_irqs = dpu_hw_intr_clear_irqs; ops->disable_all_irqs = dpu_hw_intr_disable_irqs; - ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses; - ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock; ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status; + ops->lock = dpu_hw_intr_lock; + ops->unlock = dpu_hw_intr_unlock; } static void __intr_offset(struct dpu_mdss_cfg *m, @@ -1701,7 +423,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, __intr_offset(m, addr, &intr->hw); __setup_intr_ops(&intr->ops); - intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map); + intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32; intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), GFP_KERNEL); @@ -1710,16 +432,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, return ERR_PTR(-ENOMEM); } - intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), - GFP_KERNEL); - if (intr->save_irq_status == NULL) { - kfree(intr->cache_irq_mask); - kfree(intr); - return ERR_PTR(-ENOMEM); - } - intr->irq_mask = m->mdss_irqs; - intr->obsolete_irq = m->obsolete_irq; spin_lock_init(&intr->irq_lock); @@ -1730,7 +443,6 @@ void dpu_hw_intr_destroy(struct dpu_hw_intr *intr) { if (intr) { kfree(intr->cache_irq_mask); - kfree(intr->save_irq_status); kfree(intr); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 5d6f9a7a5195..ac83c1159815 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -12,85 +12,32 @@ #include "dpu_hw_util.h" #include "dpu_hw_mdss.h" -/** - * dpu_intr_type - HW Interrupt Type - * @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done - * @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done - * @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done - * @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer - * @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer - * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh - * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check - * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection - * @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun - * @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC - * @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow - * @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done - * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset - * @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done - * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset - * @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer - * @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static - * @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static - * @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt - * @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight - * @DPU_IRQ_TYPE_CTL_START: Control start - * @DPU_IRQ_TYPE_RESERVED: Reserved for expansion - */ -enum dpu_intr_type { - DPU_IRQ_TYPE_WB_ROT_COMP, - DPU_IRQ_TYPE_WB_WFD_COMP, - DPU_IRQ_TYPE_PING_PONG_COMP, - DPU_IRQ_TYPE_PING_PONG_RD_PTR, - DPU_IRQ_TYPE_PING_PONG_WR_PTR, - DPU_IRQ_TYPE_PING_PONG_AUTO_REF, - DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, - DPU_IRQ_TYPE_PING_PONG_TE_CHECK, - DPU_IRQ_TYPE_INTF_UNDER_RUN, - DPU_IRQ_TYPE_INTF_VSYNC, - DPU_IRQ_TYPE_CWB_OVERFLOW, - DPU_IRQ_TYPE_HIST_VIG_DONE, - DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, - DPU_IRQ_TYPE_HIST_DSPP_DONE, - DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, - DPU_IRQ_TYPE_WD_TIMER, - DPU_IRQ_TYPE_SFI_VIDEO_IN, - DPU_IRQ_TYPE_SFI_VIDEO_OUT, - DPU_IRQ_TYPE_SFI_CMD_0_IN, - DPU_IRQ_TYPE_SFI_CMD_0_OUT, - DPU_IRQ_TYPE_SFI_CMD_1_IN, - DPU_IRQ_TYPE_SFI_CMD_1_OUT, - DPU_IRQ_TYPE_SFI_CMD_2_IN, - DPU_IRQ_TYPE_SFI_CMD_2_OUT, - DPU_IRQ_TYPE_PROG_LINE, - DPU_IRQ_TYPE_AD4_BL_DONE, - DPU_IRQ_TYPE_CTL_START, - DPU_IRQ_TYPE_RESERVED, +/* When making changes be sure to sync with dpu_intr_set */ +enum dpu_hw_intr_reg { + MDP_SSPP_TOP0_INTR, + MDP_SSPP_TOP0_INTR2, + MDP_SSPP_TOP0_HIST_INTR, + MDP_INTF0_INTR, + MDP_INTF1_INTR, + MDP_INTF2_INTR, + MDP_INTF3_INTR, + MDP_INTF4_INTR, + MDP_AD4_0_INTR, + MDP_AD4_1_INTR, + MDP_INTF0_7xxx_INTR, + MDP_INTF1_7xxx_INTR, + MDP_INTF5_7xxx_INTR, + MDP_INTR_MAX, }; +#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) + struct dpu_hw_intr; /** * Interrupt operations. */ struct dpu_hw_intr_ops { - /** - * irq_idx_lookup - Lookup IRQ index on the HW interrupt type - * Used for all irq related ops - * @intr: HW interrupt handle - * @intr_type: Interrupt type defined in dpu_intr_type - * @instance_idx: HW interrupt block instance - * @return: irq_idx or -EINVAL for lookup fail - */ - int (*irq_idx_lookup)(struct dpu_hw_intr *intr, - enum dpu_intr_type intr_type, - u32 instance_idx); /** * enable_irq - Enable IRQ based on lookup IRQ index @@ -98,7 +45,7 @@ struct dpu_hw_intr_ops { * @irq_idx: Lookup irq index return from irq_idx_lookup * @return: 0 for success, otherwise failure */ - int (*enable_irq)( + int (*enable_irq_locked)( struct dpu_hw_intr *intr, int irq_idx); @@ -108,7 +55,7 @@ struct dpu_hw_intr_ops { * @irq_idx: Lookup irq index return from irq_idx_lookup * @return: 0 for success, otherwise failure */ - int (*disable_irq)( + int (*disable_irq_locked)( struct dpu_hw_intr *intr, int irq_idx); @@ -143,23 +90,6 @@ struct dpu_hw_intr_ops { void *arg); /** - * get_interrupt_statuses - Gets and store value from all interrupt - * status registers that are currently fired. - * @intr: HW interrupt handle - */ - void (*get_interrupt_statuses)( - struct dpu_hw_intr *intr); - - /** - * clear_intr_status_nolock() - clears the HW interrupts without lock - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - */ - void (*clear_intr_status_nolock)( - struct dpu_hw_intr *intr, - int irq_idx); - - /** * get_interrupt_status - Gets HW interrupt status, and clear if set, * based on given lookup IRQ index. * @intr: HW interrupt handle @@ -170,6 +100,22 @@ struct dpu_hw_intr_ops { struct dpu_hw_intr *intr, int irq_idx, bool clear); + + /** + * lock - take the IRQ lock + * @intr: HW interrupt handle + * @return: irq_flags for the taken spinlock + */ + unsigned long (*lock)( + struct dpu_hw_intr *intr); + + /** + * unlock - take the IRQ lock + * @intr: HW interrupt handle + * @irq_flags: the irq_flags returned from lock + */ + void (*unlock)( + struct dpu_hw_intr *intr, unsigned long irq_flags); }; /** @@ -178,19 +124,17 @@ struct dpu_hw_intr_ops { * @ops: function pointer mapping for IRQ handling * @cache_irq_mask: array of IRQ enable masks reg storage created during init * @save_irq_status: array of IRQ status reg storage created during init - * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts + * @total_irqs: total number of irq_idx mapped in the hw_interrupts * @irq_lock: spinlock for accessing IRQ resources - * @obsolete_irq: irq types that are obsolete for a particular target */ struct dpu_hw_intr { struct dpu_hw_blk_reg_map hw; struct dpu_hw_intr_ops ops; u32 *cache_irq_mask; u32 *save_irq_status; - u32 irq_idx_tbl_size; + u32 total_irqs; spinlock_t irq_lock; unsigned long irq_mask; - unsigned long obsolete_irq; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 1599e3f49a4f..116e2b5b1a90 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -299,8 +299,6 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -327,15 +325,11 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, c->mdss = m; _setup_intf_ops(&c->ops, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops); - return c; } void dpu_hw_intf_destroy(struct dpu_hw_intf *intf) { - if (intf) - dpu_hw_blk_destroy(&intf->base); kfree(intf); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 6ac0b5a0e057..cb6bb7a22c15 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -160,8 +160,6 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, ops->setup_border_color = dpu_hw_lm_setup_border_color; } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -184,14 +182,10 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, c->cap = cfg; _setup_mixer_ops(m, &c->ops, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); - return c; } void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) { - if (lm) - dpu_hw_blk_destroy(&lm->base); kfree(lm); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index 09a3fb3e89f5..bb9ceadeb0bb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -343,7 +343,7 @@ enum dpu_3d_blend_mode { /** struct dpu_format - defines the format configuration which * allows DPU HW to correctly fetch and decode the format - * @base: base msm_format struture containing fourcc code + * @base: base msm_format structure containing fourcc code * @fetch_planes: how the color components are packed in pixel format * @element: element color ordering * @bits: element bit widths diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c index 720813e5a8ae..c06d595d5df0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -58,8 +58,6 @@ static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -81,14 +79,10 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, c->caps = cfg; _setup_merge_3d_ops(c, c->caps->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx, &dpu_hw_ops); - return c; } void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw) { - if (hw) - dpu_hw_blk_destroy(&hw->base); kfree(hw); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 245a7a62b5c6..55766c97c4c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -261,8 +261,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, c->ops.setup_dither = dpu_hw_pp_setup_dither; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -284,14 +282,10 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, c->caps = cfg; _setup_pingpong_ops(c, c->caps->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); - return c; } void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp) { - if (pp) - dpu_hw_blk_destroy(&pp->base); kfree(pp); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index 845b9ce80e31..89d08a715c16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -126,6 +126,8 @@ struct dpu_hw_pingpong_ops { struct dpu_hw_dither_cfg *cfg); }; +struct dpu_hw_merge_3d; + struct dpu_hw_pingpong { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; @@ -133,7 +135,7 @@ struct dpu_hw_pingpong { /* pingpong */ enum dpu_pingpong idx; const struct dpu_pingpong_cfg *caps; - struct dpu_hw_blk *merge_3d; + struct dpu_hw_merge_3d *merge_3d; /* ops */ struct dpu_hw_pingpong_ops ops; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 34d81aa16041..69eed7932486 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -706,8 +706,6 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, return ERR_PTR(-ENOMEM); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, struct dpu_mdss_cfg *catalog, bool is_virtual_pipe) @@ -735,15 +733,11 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, hw_pipe->cap = cfg; _setup_layer_ops(hw_pipe, hw_pipe->cap->features); - dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); - return hw_pipe; } void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) { - if (ctx) - dpu_hw_blk_destroy(&ctx->base); kfree(ctx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 01b76766a9a8..282e3c6c6d48 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -295,8 +295,6 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, return ERR_PTR(-EINVAL); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -324,15 +322,11 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, mdp->caps = cfg; _setup_mdp_ops(&mdp->ops, mdp->caps->features); - dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); - return mdp; } void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp) { - if (mdp) - dpu_hw_blk_destroy(&mdp->base); kfree(mdp); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 93bc3575bf53..4fd913522931 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -19,6 +19,7 @@ #include "msm_drv.h" #include "msm_mmu.h" #include "msm_gem.h" +#include "disp/msm_disp_snapshot.h" #include "dpu_kms.h" #include "dpu_core_irq.h" @@ -798,6 +799,51 @@ static void dpu_irq_uninstall(struct msm_kms *kms) dpu_core_irq_uninstall(dpu_kms); } +static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms) +{ + int i; + struct dpu_kms *dpu_kms; + struct dpu_mdss_cfg *cat; + struct dpu_hw_mdp *top; + + dpu_kms = to_dpu_kms(kms); + + cat = dpu_kms->catalog; + top = dpu_kms->hw_mdp; + + pm_runtime_get_sync(&dpu_kms->pdev->dev); + + /* dump CTL sub-blocks HW regs info */ + for (i = 0; i < cat->ctl_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, + dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i); + + /* dump DSPP sub-blocks HW regs info */ + for (i = 0; i < cat->dspp_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, + dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i); + + /* dump INTF sub-blocks HW regs info */ + for (i = 0; i < cat->intf_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, + dpu_kms->mmio + cat->intf[i].base, "intf_%d", i); + + /* dump PP sub-blocks HW regs info */ + for (i = 0; i < cat->pingpong_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, + dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i); + + /* dump SSPP sub-blocks HW regs info */ + for (i = 0; i < cat->sspp_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, + dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i); + + msm_disp_snapshot_add_block(disp_state, top->hw.length, + dpu_kms->mmio + top->hw.blk_off, "top"); + + pm_runtime_put_sync(&dpu_kms->pdev->dev); +} + static const struct msm_kms_funcs kms_funcs = { .hw_init = dpu_kms_hw_init, .irq_preinstall = dpu_irq_preinstall, @@ -818,6 +864,7 @@ static const struct msm_kms_funcs kms_funcs = { .round_pixclk = dpu_kms_round_pixclk, .destroy = dpu_kms_destroy, .set_encoder_mode = _dpu_kms_set_encoder_mode, + .snapshot = dpu_kms_mdp_snapshot, #ifdef CONFIG_DEBUG_FS .debugfs_init = dpu_kms_debugfs_init, #endif @@ -1089,21 +1136,21 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) if (!dpu_kms) return -ENOMEM; - dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core"); - if (IS_ERR(dpu_kms->opp_table)) - return PTR_ERR(dpu_kms->opp_table); + ret = devm_pm_opp_set_clkname(dev, "core"); + if (ret) + return ret; /* OPP table is optional */ - ret = dev_pm_opp_of_add_table(dev); + ret = devm_pm_opp_of_add_table(dev); if (ret && ret != -ENODEV) { dev_err(dev, "invalid OPP table in device tree\n"); - goto put_clkname; + return ret; } mp = &dpu_kms->mp; ret = msm_dss_parse_clock(pdev, mp); if (ret) { DPU_ERROR("failed to parse clocks, ret=%d\n", ret); - goto err; + return ret; } platform_set_drvdata(pdev, dpu_kms); @@ -1111,7 +1158,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) ret = msm_kms_init(&dpu_kms->base, &kms_funcs); if (ret) { DPU_ERROR("failed to init kms, ret=%d\n", ret); - goto err; + return ret; } dpu_kms->dev = ddev; dpu_kms->pdev = pdev; @@ -1120,11 +1167,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) dpu_kms->rpm_enabled = true; priv->kms = &dpu_kms->base; - return ret; -err: - dev_pm_opp_of_remove_table(dev); -put_clkname: - dev_pm_opp_put_clkname(dpu_kms->opp_table); + return ret; } @@ -1140,9 +1183,6 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data) if (dpu_kms->rpm_enabled) pm_runtime_disable(&pdev->dev); - - dev_pm_opp_of_remove_table(dev); - dev_pm_opp_put_clkname(dpu_kms->opp_table); } static const struct component_ops dpu_ops = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d6717d6672f7..323a6bce9e64 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -82,16 +82,12 @@ struct dpu_irq_callback { * struct dpu_irq: IRQ structure contains callback registration info * @total_irq: total number of irq_idx obtained from HW interrupts mapping * @irq_cb_tbl: array of IRQ callbacks setting - * @enable_counts array of IRQ enable counts - * @cb_lock: callback lock * @debugfs_file: debugfs file for irq statistics */ struct dpu_irq { u32 total_irqs; struct list_head *irq_cb_tbl; - atomic_t *enable_counts; atomic_t *irq_counts; - spinlock_t cb_lock; }; struct dpu_kms { @@ -130,8 +126,6 @@ struct dpu_kms { struct platform_device *pdev; bool rpm_enabled; - struct opp_table *opp_table; - struct dss_module_power mp; /* reference count bandwidth requests, so we know when we can @@ -258,7 +252,7 @@ void dpu_kms_encoder_enable(struct drm_encoder *encoder); /** * dpu_kms_get_clk_rate() - get the clock rate - * @dpu_kms: poiner to dpu_kms structure + * @dpu_kms: pointer to dpu_kms structure * @clock_name: clock name to get the rate * * Return: current clock rate diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c index 06b56fec04e0..6b0a7bc87eb7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c @@ -225,7 +225,7 @@ int dpu_mdss_init(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct dpu_mdss *dpu_mdss; struct dss_module_power *mp; - int ret = 0; + int ret; int irq; dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL); @@ -253,8 +253,10 @@ int dpu_mdss_init(struct drm_device *dev) goto irq_domain_error; irq = platform_get_irq(pdev, 0); - if (irq < 0) + if (irq < 0) { + ret = irq; goto irq_error; + } irq_set_chained_handler_and_data(irq, dpu_mdss_irq, dpu_mdss); @@ -263,7 +265,7 @@ int dpu_mdss_init(struct drm_device *dev) pm_runtime_enable(dev->dev); - return ret; + return 0; irq_error: _dpu_mdss_irq_domain_fini(dpu_mdss); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 7a993547eb75..ec4a6f04394a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -25,7 +25,7 @@ #include "dpu_vbif.h" #include "dpu_plane.h" -#define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\ +#define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ @@ -284,8 +284,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, } } - DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n", - plane->base.id, pdpu->pipe - SSPP_VIG0, + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", + pdpu->pipe - SSPP_VIG0, (char *)&fmt->base.pixel_format, src_width, total_fl); @@ -354,8 +354,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, (fmt) ? fmt->base.pixel_format : 0, pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); - DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", - plane->base.id, + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", pdpu->pipe - SSPP_VIG0, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); @@ -364,7 +363,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, } /** - * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane + * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane * @plane: Pointer to drm plane * @fb: Pointer to framebuffer associated with the given plane */ @@ -407,8 +406,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, pdpu->pipe_qos_cfg.danger_lut, pdpu->pipe_qos_cfg.safe_lut); - DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", - plane->base.id, + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", pdpu->pipe - SSPP_VIG0, fmt ? (char *)&fmt->base.pixel_format : NULL, fmt ? fmt->fetch_mode : -1, @@ -451,8 +449,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, pdpu->pipe_qos_cfg.danger_safe_en = false; } - DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", - plane->base.id, + DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", pdpu->pipe - SSPP_VIG0, pdpu->pipe_qos_cfg.danger_safe_en, pdpu->pipe_qos_cfg.vblank_en, @@ -491,7 +488,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, } /** - * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane + * _dpu_plane_set_qos_remap - set vbif QoS for the given plane * @plane: Pointer to drm plane */ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) @@ -507,8 +504,8 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; - DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", - plane->base.id, qos_params.num, + DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", + qos_params.num, qos_params.vbif_idx, qos_params.xin_id, qos_params.is_rt, qos_params.clk_ctrl); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index fd2d104f0a91..f9c83d6e427a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -162,7 +162,7 @@ int dpu_rm_init(struct dpu_rm *rm, goto fail; } if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX) - hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]; + hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]); rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base; } @@ -428,7 +428,7 @@ static int _dpu_rm_reserve_ctls( features = ctl->caps->features; has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features; - DPU_DEBUG("ctl %d caps 0x%lX\n", rm->ctl_blks[j]->id, features); + DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features); if (needs_split_display != has_split_display) continue; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 6714b088970f..37bba57675a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -168,44 +168,41 @@ TRACE_EVENT(dpu_perf_crtc_update, ); DECLARE_EVENT_CLASS(dpu_enc_irq_template, - TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, + TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int irq_idx), - TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx), + TP_ARGS(drm_id, intr_idx, irq_idx), TP_STRUCT__entry( __field( uint32_t, drm_id ) __field( enum dpu_intr_idx, intr_idx ) - __field( int, hw_idx ) __field( int, irq_idx ) ), TP_fast_assign( __entry->drm_id = drm_id; __entry->intr_idx = intr_idx; - __entry->hw_idx = hw_idx; __entry->irq_idx = irq_idx; ), - TP_printk("id=%u, intr=%d, hw=%d, irq=%d", - __entry->drm_id, __entry->intr_idx, __entry->hw_idx, + TP_printk("id=%u, intr=%d, irq=%d", + __entry->drm_id, __entry->intr_idx, __entry->irq_idx) ); DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success, - TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, + TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int irq_idx), - TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx) + TP_ARGS(drm_id, intr_idx, irq_idx) ); DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success, - TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, + TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int irq_idx), - TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx) + TP_ARGS(drm_id, intr_idx, irq_idx) ); TRACE_EVENT(dpu_enc_irq_wait_success, - TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, + TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt), - TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt), + TP_ARGS(drm_id, intr_idx, irq_idx, pp_idx, atomic_cnt), TP_STRUCT__entry( __field( uint32_t, drm_id ) __field( enum dpu_intr_idx, intr_idx ) - __field( int, hw_idx ) __field( int, irq_idx ) __field( enum dpu_pingpong, pp_idx ) __field( int, atomic_cnt ) @@ -213,13 +210,12 @@ TRACE_EVENT(dpu_enc_irq_wait_success, TP_fast_assign( __entry->drm_id = drm_id; __entry->intr_idx = intr_idx; - __entry->hw_idx = hw_idx; __entry->irq_idx = irq_idx; __entry->pp_idx = pp_idx; __entry->atomic_cnt = atomic_cnt; ), - TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d", - __entry->drm_id, __entry->intr_idx, __entry->hw_idx, + TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d", + __entry->drm_id, __entry->intr_idx, __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt) ); @@ -514,12 +510,12 @@ DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending, ); TRACE_EVENT(dpu_enc_wait_event_timeout, - TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time, + TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time, s64 expected_time, int atomic_cnt), - TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt), + TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt), TP_STRUCT__entry( __field( uint32_t, drm_id ) - __field( int32_t, hw_id ) + __field( int, irq_idx ) __field( int, rc ) __field( s64, time ) __field( s64, expected_time ) @@ -527,14 +523,14 @@ TRACE_EVENT(dpu_enc_wait_event_timeout, ), TP_fast_assign( __entry->drm_id = drm_id; - __entry->hw_id = hw_id; + __entry->irq_idx = irq_idx; __entry->rc = rc; __entry->time = time; __entry->expected_time = expected_time; __entry->atomic_cnt = atomic_cnt; ), - TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d", - __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time, + TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d", + __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time, __entry->expected_time, __entry->atomic_cnt) ); @@ -879,29 +875,6 @@ TRACE_EVENT(dpu_pp_connect_ext_te, TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg) ); -DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template, - TP_PROTO(int irq_idx, int enable_count), - TP_ARGS(irq_idx, enable_count), - TP_STRUCT__entry( - __field( int, irq_idx ) - __field( int, enable_count ) - ), - TP_fast_assign( - __entry->irq_idx = irq_idx; - __entry->enable_count = enable_count; - ), - TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx, - __entry->enable_count) -); -DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx, - TP_PROTO(int irq_idx, int enable_count), - TP_ARGS(irq_idx, enable_count) -); -DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx, - TP_PROTO(int irq_idx, int enable_count), - TP_ARGS(irq_idx, enable_count) -); - DECLARE_EVENT_CLASS(dpu_core_irq_callback_template, TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), TP_ARGS(irq_idx, callback), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c index 7e08f40e7e6f..21d20373eb8b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c @@ -46,7 +46,7 @@ static int _dpu_vbif_wait_for_xin_halt(struct dpu_hw_vbif *vbif, u32 xin_id) vbif->idx - VBIF_0, xin_id); } else { rc = 0; - DPU_DEBUG("VBIF %d client %d is halted\n", + DRM_DEBUG_ATOMIC("VBIF %d client %d is halted\n", vbif->idx - VBIF_0, xin_id); } @@ -87,7 +87,7 @@ static void _dpu_vbif_apply_dynamic_ot_limit(struct dpu_hw_vbif *vbif, } } - DPU_DEBUG("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n", + DRM_DEBUG_ATOMIC("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n", vbif->idx - VBIF_0, params->xin_id, params->width, params->height, params->frame_rate, pps, *ot_lim); @@ -133,7 +133,7 @@ static u32 _dpu_vbif_get_ot_limit(struct dpu_hw_vbif *vbif, } exit: - DPU_DEBUG("vbif:%d xin:%d ot_lim:%d\n", + DRM_DEBUG_ATOMIC("vbif:%d xin:%d ot_lim:%d\n", vbif->idx - VBIF_0, params->xin_id, ot_lim); return ot_lim; } @@ -163,7 +163,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, } if (!vbif || !mdp) { - DPU_DEBUG("invalid arguments vbif %d mdp %d\n", + DRM_DEBUG_ATOMIC("invalid arguments vbif %d mdp %d\n", vbif != NULL, mdp != NULL); return; } @@ -230,7 +230,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, } if (!vbif->ops.set_qos_remap || !mdp->ops.setup_clk_force_ctrl) { - DPU_DEBUG("qos remap not supported\n"); + DRM_DEBUG_ATOMIC("qos remap not supported\n"); return; } @@ -238,14 +238,14 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, &vbif->cap->qos_nrt_tbl; if (!qos_tbl->npriority_lvl || !qos_tbl->priority_lvl) { - DPU_DEBUG("qos tbl not defined\n"); + DRM_DEBUG_ATOMIC("qos tbl not defined\n"); return; } forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); for (i = 0; i < qos_tbl->npriority_lvl; i++) { - DPU_DEBUG("vbif:%d xin:%d lvl:%d/%d\n", + DRM_DEBUG_ATOMIC("vbif:%d xin:%d lvl:%d/%d\n", params->vbif_idx, params->xin_id, i, qos_tbl->priority_lvl[i]); vbif->ops.set_qos_remap(vbif, params->xin_id, i, |