diff options
Diffstat (limited to 'include')
25 files changed, 1012 insertions, 718 deletions
diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h index 06f198ee7623..2ce1a06dc735 100644 --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h @@ -164,5 +164,6 @@ #define CLKID_DMC_SEL 151 #define CLKID_DMC_DIV 152 #define CLKID_DMC_SEL2 153 +#define CLKID_SYS_PLL_DIV16 154 #endif /* __A1_PERIPHERALS_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h index 2b660c0f2c9f..0dfc5e78a2d5 100644 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h @@ -21,5 +21,6 @@ #define CLKID_FCLK_DIV5 8 #define CLKID_FCLK_DIV7 9 #define CLKID_HIFI_PLL 10 +#define CLKID_SYS_PLL 11 #endif /* __A1_PLL_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h new file mode 100644 index 000000000000..d115c741c255 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu <chuan.liu@amlogic.com> + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H + +#define CLKID_RTC_XTAL_CLKIN 0 +#define CLKID_RTC_32K_DIV 1 +#define CLKID_RTC_32K_MUX 2 +#define CLKID_RTC_32K 3 +#define CLKID_RTC_CLK 4 +#define CLKID_SYS_RESET_CTRL 5 +#define CLKID_SYS_PWR_CTRL 6 +#define CLKID_SYS_PAD_CTRL 7 +#define CLKID_SYS_CTRL 8 +#define CLKID_SYS_TS_PLL 9 +#define CLKID_SYS_DEV_ARB 10 +#define CLKID_SYS_MMC_PCLK 11 +#define CLKID_SYS_CPU_CTRL 12 +#define CLKID_SYS_JTAG_CTRL 13 +#define CLKID_SYS_IR_CTRL 14 +#define CLKID_SYS_IRQ_CTRL 15 +#define CLKID_SYS_MSR_CLK 16 +#define CLKID_SYS_ROM 17 +#define CLKID_SYS_UART_F 18 +#define CLKID_SYS_CPU_ARB 19 +#define CLKID_SYS_RSA 20 +#define CLKID_SYS_SAR_ADC 21 +#define CLKID_SYS_STARTUP 22 +#define CLKID_SYS_SECURE 23 +#define CLKID_SYS_SPIFC 24 +#define CLKID_SYS_NNA 25 +#define CLKID_SYS_ETH_MAC 26 +#define CLKID_SYS_GIC 27 +#define CLKID_SYS_RAMA 28 +#define CLKID_SYS_BIG_NIC 29 +#define CLKID_SYS_RAMB 30 +#define CLKID_SYS_AUDIO_PCLK 31 +#define CLKID_SYS_PWM_KL 32 +#define CLKID_SYS_PWM_IJ 33 +#define CLKID_SYS_USB 34 +#define CLKID_SYS_SD_EMMC_A 35 +#define CLKID_SYS_SD_EMMC_C 36 +#define CLKID_SYS_PWM_AB 37 +#define CLKID_SYS_PWM_CD 38 +#define CLKID_SYS_PWM_EF 39 +#define CLKID_SYS_PWM_GH 40 +#define CLKID_SYS_SPICC_1 41 +#define CLKID_SYS_SPICC_0 42 +#define CLKID_SYS_UART_A 43 +#define CLKID_SYS_UART_B 44 +#define CLKID_SYS_UART_C 45 +#define CLKID_SYS_UART_D 46 +#define CLKID_SYS_UART_E 47 +#define CLKID_SYS_I2C_M_A 48 +#define CLKID_SYS_I2C_M_B 49 +#define CLKID_SYS_I2C_M_C 50 +#define CLKID_SYS_I2C_M_D 51 +#define CLKID_SYS_I2S_S_A 52 +#define CLKID_SYS_RTC 53 +#define CLKID_SYS_GE2D 54 +#define CLKID_SYS_ISP 55 +#define CLKID_SYS_GPV_ISP_NIC 56 +#define CLKID_SYS_GPV_CVE_NIC 57 +#define CLKID_SYS_MIPI_DSI_HOST 58 +#define CLKID_SYS_MIPI_DSI_PHY 59 +#define CLKID_SYS_ETH_PHY 60 +#define CLKID_SYS_ACODEC 61 +#define CLKID_SYS_DWAP 62 +#define CLKID_SYS_DOS 63 +#define CLKID_SYS_CVE 64 +#define CLKID_SYS_VOUT 65 +#define CLKID_SYS_VC9000E 66 +#define CLKID_SYS_PWM_MN 67 +#define CLKID_SYS_SD_EMMC_B 68 +#define CLKID_AXI_SYS_NIC 69 +#define CLKID_AXI_ISP_NIC 70 +#define CLKID_AXI_CVE_NIC 71 +#define CLKID_AXI_RAMB 72 +#define CLKID_AXI_RAMA 73 +#define CLKID_AXI_CPU_DMC 74 +#define CLKID_AXI_NIC 75 +#define CLKID_AXI_DMA 76 +#define CLKID_AXI_MUX_NIC 77 +#define CLKID_AXI_CVE 78 +#define CLKID_AXI_DEV1_DMC 79 +#define CLKID_AXI_DEV0_DMC 80 +#define CLKID_AXI_DSP_DMC 81 +#define CLKID_12_24M_IN 82 +#define CLKID_12M_24M 83 +#define CLKID_FCLK_25M_DIV 84 +#define CLKID_FCLK_25M 85 +#define CLKID_GEN_SEL 86 +#define CLKID_GEN_DIV 87 +#define CLKID_GEN 88 +#define CLKID_SARADC_SEL 89 +#define CLKID_SARADC_DIV 90 +#define CLKID_SARADC 91 +#define CLKID_PWM_A_SEL 92 +#define CLKID_PWM_A_DIV 93 +#define CLKID_PWM_A 94 +#define CLKID_PWM_B_SEL 95 +#define CLKID_PWM_B_DIV 96 +#define CLKID_PWM_B 97 +#define CLKID_PWM_C_SEL 98 +#define CLKID_PWM_C_DIV 99 +#define CLKID_PWM_C 100 +#define CLKID_PWM_D_SEL 101 +#define CLKID_PWM_D_DIV 102 +#define CLKID_PWM_D 103 +#define CLKID_PWM_E_SEL 104 +#define CLKID_PWM_E_DIV 105 +#define CLKID_PWM_E 106 +#define CLKID_PWM_F_SEL 107 +#define CLKID_PWM_F_DIV 108 +#define CLKID_PWM_F 109 +#define CLKID_PWM_G_SEL 110 +#define CLKID_PWM_G_DIV 111 +#define CLKID_PWM_G 112 +#define CLKID_PWM_H_SEL 113 +#define CLKID_PWM_H_DIV 114 +#define CLKID_PWM_H 115 +#define CLKID_PWM_I_SEL 116 +#define CLKID_PWM_I_DIV 117 +#define CLKID_PWM_I 118 +#define CLKID_PWM_J_SEL 119 +#define CLKID_PWM_J_DIV 120 +#define CLKID_PWM_J 121 +#define CLKID_PWM_K_SEL 122 +#define CLKID_PWM_K_DIV 123 +#define CLKID_PWM_K 124 +#define CLKID_PWM_L_SEL 125 +#define CLKID_PWM_L_DIV 126 +#define CLKID_PWM_L 127 +#define CLKID_PWM_M_SEL 128 +#define CLKID_PWM_M_DIV 129 +#define CLKID_PWM_M 130 +#define CLKID_PWM_N_SEL 131 +#define CLKID_PWM_N_DIV 132 +#define CLKID_PWM_N 133 +#define CLKID_SPICC_A_SEL 134 +#define CLKID_SPICC_A_DIV 135 +#define CLKID_SPICC_A 136 +#define CLKID_SPICC_B_SEL 137 +#define CLKID_SPICC_B_DIV 138 +#define CLKID_SPICC_B 139 +#define CLKID_SPIFC_SEL 140 +#define CLKID_SPIFC_DIV 141 +#define CLKID_SPIFC 142 +#define CLKID_SD_EMMC_A_SEL 143 +#define CLKID_SD_EMMC_A_DIV 144 +#define CLKID_SD_EMMC_A 145 +#define CLKID_SD_EMMC_B_SEL 146 +#define CLKID_SD_EMMC_B_DIV 147 +#define CLKID_SD_EMMC_B 148 +#define CLKID_SD_EMMC_C_SEL 149 +#define CLKID_SD_EMMC_C_DIV 150 +#define CLKID_SD_EMMC_C 151 +#define CLKID_TS_DIV 152 +#define CLKID_TS 153 +#define CLKID_ETH_125M_DIV 154 +#define CLKID_ETH_125M 155 +#define CLKID_ETH_RMII_DIV 156 +#define CLKID_ETH_RMII 157 +#define CLKID_MIPI_DSI_MEAS_SEL 158 +#define CLKID_MIPI_DSI_MEAS_DIV 159 +#define CLKID_MIPI_DSI_MEAS 160 +#define CLKID_DSI_PHY_SEL 161 +#define CLKID_DSI_PHY_DIV 162 +#define CLKID_DSI_PHY 163 +#define CLKID_VOUT_MCLK_SEL 164 +#define CLKID_VOUT_MCLK_DIV 165 +#define CLKID_VOUT_MCLK 166 +#define CLKID_VOUT_ENC_SEL 167 +#define CLKID_VOUT_ENC_DIV 168 +#define CLKID_VOUT_ENC 169 +#define CLKID_HCODEC_0_SEL 170 +#define CLKID_HCODEC_0_DIV 171 +#define CLKID_HCODEC_0 172 +#define CLKID_HCODEC_1_SEL 173 +#define CLKID_HCODEC_1_DIV 174 +#define CLKID_HCODEC_1 175 +#define CLKID_HCODEC 176 +#define CLKID_VC9000E_ACLK_SEL 177 +#define CLKID_VC9000E_ACLK_DIV 178 +#define CLKID_VC9000E_ACLK 179 +#define CLKID_VC9000E_CORE_SEL 180 +#define CLKID_VC9000E_CORE_DIV 181 +#define CLKID_VC9000E_CORE 182 +#define CLKID_CSI_PHY0_SEL 183 +#define CLKID_CSI_PHY0_DIV 184 +#define CLKID_CSI_PHY0 185 +#define CLKID_DEWARPA_SEL 186 +#define CLKID_DEWARPA_DIV 187 +#define CLKID_DEWARPA 188 +#define CLKID_ISP0_SEL 189 +#define CLKID_ISP0_DIV 190 +#define CLKID_ISP0 191 +#define CLKID_NNA_CORE_SEL 192 +#define CLKID_NNA_CORE_DIV 193 +#define CLKID_NNA_CORE 194 +#define CLKID_GE2D_SEL 195 +#define CLKID_GE2D_DIV 196 +#define CLKID_GE2D 197 +#define CLKID_VAPB_SEL 198 +#define CLKID_VAPB_DIV 199 +#define CLKID_VAPB 200 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h new file mode 100644 index 000000000000..fcdc558715e8 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu <chuan.liu@amlogic.com> + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H + +#define CLKID_FCLK_50M_EN 0 +#define CLKID_FCLK_50M 1 +#define CLKID_FCLK_DIV2_DIV 2 +#define CLKID_FCLK_DIV2 3 +#define CLKID_FCLK_DIV2P5_DIV 4 +#define CLKID_FCLK_DIV2P5 5 +#define CLKID_FCLK_DIV3_DIV 6 +#define CLKID_FCLK_DIV3 7 +#define CLKID_FCLK_DIV4_DIV 8 +#define CLKID_FCLK_DIV4 9 +#define CLKID_FCLK_DIV5_DIV 10 +#define CLKID_FCLK_DIV5 11 +#define CLKID_FCLK_DIV7_DIV 12 +#define CLKID_FCLK_DIV7 13 +#define CLKID_GP0_PLL_DCO 14 +#define CLKID_GP0_PLL 15 +#define CLKID_HIFI_PLL_DCO 16 +#define CLKID_HIFI_PLL 17 +#define CLKID_MCLK_PLL_DCO 18 +#define CLKID_MCLK_PLL_OD 19 +#define CLKID_MCLK_PLL 20 +#define CLKID_MCLK0_SEL 21 +#define CLKID_MCLK0_SEL_EN 22 +#define CLKID_MCLK0_DIV 23 +#define CLKID_MCLK0 24 +#define CLKID_MCLK1_SEL 25 +#define CLKID_MCLK1_SEL_EN 26 +#define CLKID_MCLK1_DIV 27 +#define CLKID_MCLK1 28 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,c3-scmi-clkc.h b/include/dt-bindings/clock/amlogic,c3-scmi-clkc.h new file mode 100644 index 000000000000..663c9b349275 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,c3-scmi-clkc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu <chuan.liu@amlogic.com> + */ + +#ifndef __AMLOGIC_C3_SCMI_CLKC_H +#define __AMLOGIC_C3_SCMI_CLKC_H + +#define CLKID_DDR_PLL_OSC 0 +#define CLKID_DDR_PHY 1 +#define CLKID_TOP_PLL_OSC 2 +#define CLKID_USB_PLL_OSC 3 +#define CLKID_MIPIISP_VOUT 4 +#define CLKID_MCLK_PLL_OSC 5 +#define CLKID_USB_CTRL 6 +#define CLKID_ETH_PLL_OSC 7 +#define CLKID_OSC 8 +#define CLKID_SYS_CLK 9 +#define CLKID_AXI_CLK 10 +#define CLKID_CPU_CLK 11 +#define CLKID_FIXED_PLL_OSC 12 +#define CLKID_GP1_PLL_OSC 13 +#define CLKID_SYS_PLL_DIV16 14 +#define CLKID_CPU_CLK_DIV16 15 + +#endif /* __AMLOGIC_C3_SCMI_CLKC_H */ diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 08fd3a37acaa..52123c5a09fa 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -216,4 +216,8 @@ #define GCC_CRYPTO_AHB_CLK 207 #define GCC_USB0_PIPE_CLK 208 #define GCC_USB0_SLEEP_CLK 209 +#define GCC_PCIE0_PIPE_CLK 210 +#define GCC_PCIE1_PIPE_CLK 211 +#define GCC_PCIE2_PIPE_CLK 212 +#define GCC_PCIE3_PIPE_CLK 213 #endif diff --git a/include/dt-bindings/clock/qcom,qca8k-nsscc.h b/include/dt-bindings/clock/qcom,qca8k-nsscc.h new file mode 100644 index 000000000000..0ac3e4c69a1a --- /dev/null +++ b/include/dt-bindings/clock/qcom,qca8k-nsscc.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H +#define _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H + +#define NSS_CC_SWITCH_CORE_CLK_SRC 0 +#define NSS_CC_SWITCH_CORE_CLK 1 +#define NSS_CC_APB_BRIDGE_CLK 2 +#define NSS_CC_MAC0_TX_CLK_SRC 3 +#define NSS_CC_MAC0_TX_DIV_CLK_SRC 4 +#define NSS_CC_MAC0_TX_CLK 5 +#define NSS_CC_MAC0_TX_SRDS1_CLK 6 +#define NSS_CC_MAC0_RX_CLK_SRC 7 +#define NSS_CC_MAC0_RX_DIV_CLK_SRC 8 +#define NSS_CC_MAC0_RX_CLK 9 +#define NSS_CC_MAC0_RX_SRDS1_CLK 10 +#define NSS_CC_MAC1_TX_CLK_SRC 11 +#define NSS_CC_MAC1_TX_DIV_CLK_SRC 12 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC 13 +#define NSS_CC_MAC1_SRDS1_CH0_RX_CLK 14 +#define NSS_CC_MAC1_TX_CLK 15 +#define NSS_CC_MAC1_GEPHY0_TX_CLK 16 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK 17 +#define NSS_CC_MAC1_RX_CLK_SRC 18 +#define NSS_CC_MAC1_RX_DIV_CLK_SRC 19 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC 20 +#define NSS_CC_MAC1_SRDS1_CH0_TX_CLK 21 +#define NSS_CC_MAC1_RX_CLK 22 +#define NSS_CC_MAC1_GEPHY0_RX_CLK 23 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK 24 +#define NSS_CC_MAC2_TX_CLK_SRC 25 +#define NSS_CC_MAC2_TX_DIV_CLK_SRC 26 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC 27 +#define NSS_CC_MAC2_SRDS1_CH1_RX_CLK 28 +#define NSS_CC_MAC2_TX_CLK 29 +#define NSS_CC_MAC2_GEPHY1_TX_CLK 30 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK 31 +#define NSS_CC_MAC2_RX_CLK_SRC 32 +#define NSS_CC_MAC2_RX_DIV_CLK_SRC 33 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC 34 +#define NSS_CC_MAC2_SRDS1_CH1_TX_CLK 35 +#define NSS_CC_MAC2_RX_CLK 36 +#define NSS_CC_MAC2_GEPHY1_RX_CLK 37 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK 38 +#define NSS_CC_MAC3_TX_CLK_SRC 39 +#define NSS_CC_MAC3_TX_DIV_CLK_SRC 40 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC 41 +#define NSS_CC_MAC3_SRDS1_CH2_RX_CLK 42 +#define NSS_CC_MAC3_TX_CLK 43 +#define NSS_CC_MAC3_GEPHY2_TX_CLK 44 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK 45 +#define NSS_CC_MAC3_RX_CLK_SRC 46 +#define NSS_CC_MAC3_RX_DIV_CLK_SRC 47 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC 48 +#define NSS_CC_MAC3_SRDS1_CH2_TX_CLK 49 +#define NSS_CC_MAC3_RX_CLK 50 +#define NSS_CC_MAC3_GEPHY2_RX_CLK 51 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK 52 +#define NSS_CC_MAC4_TX_CLK_SRC 53 +#define NSS_CC_MAC4_TX_DIV_CLK_SRC 54 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC 55 +#define NSS_CC_MAC4_SRDS1_CH3_RX_CLK 56 +#define NSS_CC_MAC4_TX_CLK 57 +#define NSS_CC_MAC4_GEPHY3_TX_CLK 58 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK 59 +#define NSS_CC_MAC4_RX_CLK_SRC 60 +#define NSS_CC_MAC4_RX_DIV_CLK_SRC 61 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC 62 +#define NSS_CC_MAC4_SRDS1_CH3_TX_CLK 63 +#define NSS_CC_MAC4_RX_CLK 64 +#define NSS_CC_MAC4_GEPHY3_RX_CLK 65 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK 66 +#define NSS_CC_MAC5_TX_CLK_SRC 67 +#define NSS_CC_MAC5_TX_DIV_CLK_SRC 68 +#define NSS_CC_MAC5_TX_SRDS0_CLK 69 +#define NSS_CC_MAC5_TX_CLK 70 +#define NSS_CC_MAC5_RX_CLK_SRC 71 +#define NSS_CC_MAC5_RX_DIV_CLK_SRC 72 +#define NSS_CC_MAC5_RX_SRDS0_CLK 73 +#define NSS_CC_MAC5_RX_CLK 74 +#define NSS_CC_MAC5_TX_SRDS0_CLK_SRC 75 +#define NSS_CC_MAC5_RX_SRDS0_CLK_SRC 76 +#define NSS_CC_AHB_CLK_SRC 77 +#define NSS_CC_AHB_CLK 78 +#define NSS_CC_SEC_CTRL_AHB_CLK 79 +#define NSS_CC_TLMM_CLK 80 +#define NSS_CC_TLMM_AHB_CLK 81 +#define NSS_CC_CNOC_AHB_CLK 82 +#define NSS_CC_MDIO_AHB_CLK 83 +#define NSS_CC_MDIO_MASTER_AHB_CLK 84 +#define NSS_CC_SYS_CLK_SRC 85 +#define NSS_CC_SRDS0_SYS_CLK 86 +#define NSS_CC_SRDS1_SYS_CLK 87 +#define NSS_CC_GEPHY0_SYS_CLK 88 +#define NSS_CC_GEPHY1_SYS_CLK 89 +#define NSS_CC_GEPHY2_SYS_CLK 90 +#define NSS_CC_GEPHY3_SYS_CLK 91 +#endif diff --git a/include/dt-bindings/clock/qcom,sm7150-camcc.h b/include/dt-bindings/clock/qcom,sm7150-camcc.h new file mode 100644 index 000000000000..ce73ef0fe95d --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7150-camcc.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H +#define _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H + +/* Hardware clocks */ +#define CAMCC_PLL0_OUT_EVEN 0 +#define CAMCC_PLL0_OUT_ODD 1 +#define CAMCC_PLL1_OUT_EVEN 2 +#define CAMCC_PLL2_OUT_EARLY 3 +#define CAMCC_PLL3_OUT_EVEN 4 +#define CAMCC_PLL4_OUT_EVEN 5 + +/* CAMCC clock registers */ +#define CAMCC_PLL0 6 +#define CAMCC_PLL1 7 +#define CAMCC_PLL2 8 +#define CAMCC_PLL2_OUT_AUX 9 +#define CAMCC_PLL2_OUT_MAIN 10 +#define CAMCC_PLL3 11 +#define CAMCC_PLL4 12 +#define CAMCC_BPS_AHB_CLK 13 +#define CAMCC_BPS_AREG_CLK 14 +#define CAMCC_BPS_AXI_CLK 15 +#define CAMCC_BPS_CLK 16 +#define CAMCC_BPS_CLK_SRC 17 +#define CAMCC_CAMNOC_AXI_CLK 18 +#define CAMCC_CAMNOC_AXI_CLK_SRC 19 +#define CAMCC_CAMNOC_DCD_XO_CLK 20 +#define CAMCC_CCI_0_CLK 21 +#define CAMCC_CCI_0_CLK_SRC 22 +#define CAMCC_CCI_1_CLK 23 +#define CAMCC_CCI_1_CLK_SRC 24 +#define CAMCC_CORE_AHB_CLK 25 +#define CAMCC_CPAS_AHB_CLK 26 +#define CAMCC_CPHY_RX_CLK_SRC 27 +#define CAMCC_CSI0PHYTIMER_CLK 28 +#define CAMCC_CSI0PHYTIMER_CLK_SRC 29 +#define CAMCC_CSI1PHYTIMER_CLK 30 +#define CAMCC_CSI1PHYTIMER_CLK_SRC 31 +#define CAMCC_CSI2PHYTIMER_CLK 32 +#define CAMCC_CSI2PHYTIMER_CLK_SRC 33 +#define CAMCC_CSI3PHYTIMER_CLK 34 +#define CAMCC_CSI3PHYTIMER_CLK_SRC 35 +#define CAMCC_CSIPHY0_CLK 36 +#define CAMCC_CSIPHY1_CLK 37 +#define CAMCC_CSIPHY2_CLK 38 +#define CAMCC_CSIPHY3_CLK 39 +#define CAMCC_FAST_AHB_CLK_SRC 40 +#define CAMCC_FD_CORE_CLK 41 +#define CAMCC_FD_CORE_CLK_SRC 42 +#define CAMCC_FD_CORE_UAR_CLK 43 +#define CAMCC_ICP_AHB_CLK 44 +#define CAMCC_ICP_CLK 45 +#define CAMCC_ICP_CLK_SRC 46 +#define CAMCC_IFE_0_AXI_CLK 47 +#define CAMCC_IFE_0_CLK 48 +#define CAMCC_IFE_0_CLK_SRC 49 +#define CAMCC_IFE_0_CPHY_RX_CLK 50 +#define CAMCC_IFE_0_CSID_CLK 51 +#define CAMCC_IFE_0_CSID_CLK_SRC 52 +#define CAMCC_IFE_0_DSP_CLK 53 +#define CAMCC_IFE_1_AXI_CLK 54 +#define CAMCC_IFE_1_CLK 55 +#define CAMCC_IFE_1_CLK_SRC 56 +#define CAMCC_IFE_1_CPHY_RX_CLK 57 +#define CAMCC_IFE_1_CSID_CLK 58 +#define CAMCC_IFE_1_CSID_CLK_SRC 59 +#define CAMCC_IFE_1_DSP_CLK 60 +#define CAMCC_IFE_LITE_CLK 61 +#define CAMCC_IFE_LITE_CLK_SRC 62 +#define CAMCC_IFE_LITE_CPHY_RX_CLK 63 +#define CAMCC_IFE_LITE_CSID_CLK 64 +#define CAMCC_IFE_LITE_CSID_CLK_SRC 65 +#define CAMCC_IPE_0_AHB_CLK 66 +#define CAMCC_IPE_0_AREG_CLK 67 +#define CAMCC_IPE_0_AXI_CLK 68 +#define CAMCC_IPE_0_CLK 69 +#define CAMCC_IPE_0_CLK_SRC 70 +#define CAMCC_IPE_1_AHB_CLK 71 +#define CAMCC_IPE_1_AREG_CLK 72 +#define CAMCC_IPE_1_AXI_CLK 73 +#define CAMCC_IPE_1_CLK 74 +#define CAMCC_JPEG_CLK 75 +#define CAMCC_JPEG_CLK_SRC 76 +#define CAMCC_LRME_CLK 77 +#define CAMCC_LRME_CLK_SRC 78 +#define CAMCC_MCLK0_CLK 79 +#define CAMCC_MCLK0_CLK_SRC 80 +#define CAMCC_MCLK1_CLK 81 +#define CAMCC_MCLK1_CLK_SRC 82 +#define CAMCC_MCLK2_CLK 83 +#define CAMCC_MCLK2_CLK_SRC 84 +#define CAMCC_MCLK3_CLK 85 +#define CAMCC_MCLK3_CLK_SRC 86 +#define CAMCC_SLEEP_CLK 87 +#define CAMCC_SLEEP_CLK_SRC 88 +#define CAMCC_SLOW_AHB_CLK_SRC 89 +#define CAMCC_XO_CLK_SRC 90 + +/* CAMCC GDSCRs */ +#define BPS_GDSC 0 +#define IFE_0_GDSC 1 +#define IFE_1_GDSC 2 +#define IPE_0_GDSC 3 +#define IPE_1_GDSC 4 +#define TITAN_TOP_GDSC 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm7150-dispcc.h b/include/dt-bindings/clock/qcom,sm7150-dispcc.h new file mode 100644 index 000000000000..fc1fefe8fd72 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7150-dispcc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> + * Copyright (c) 2024, David Wronek <david@mainlining.org> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H +#define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H + +/* DISPCC clock registers */ +#define DISPCC_PLL0 0 +#define DISPCC_MDSS_AHB_CLK 1 +#define DISPCC_MDSS_AHB_CLK_SRC 2 +#define DISPCC_MDSS_BYTE0_CLK 3 +#define DISPCC_MDSS_BYTE0_CLK_SRC 4 +#define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISPCC_MDSS_BYTE0_INTF_CLK 6 +#define DISPCC_MDSS_BYTE1_CLK 7 +#define DISPCC_MDSS_BYTE1_CLK_SRC 8 +#define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 9 +#define DISPCC_MDSS_BYTE1_INTF_CLK 10 +#define DISPCC_MDSS_DP_AUX_CLK 11 +#define DISPCC_MDSS_DP_AUX_CLK_SRC 12 +#define DISPCC_MDSS_DP_CRYPTO_CLK 13 +#define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 14 +#define DISPCC_MDSS_DP_LINK_CLK 15 +#define DISPCC_MDSS_DP_LINK_CLK_SRC 16 +#define DISPCC_MDSS_DP_LINK_INTF_CLK 17 +#define DISPCC_MDSS_DP_PIXEL1_CLK 18 +#define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 19 +#define DISPCC_MDSS_DP_PIXEL_CLK 20 +#define DISPCC_MDSS_DP_PIXEL_CLK_SRC 21 +#define DISPCC_MDSS_ESC0_CLK 22 +#define DISPCC_MDSS_ESC0_CLK_SRC 23 +#define DISPCC_MDSS_ESC1_CLK 24 +#define DISPCC_MDSS_ESC1_CLK_SRC 25 +#define DISPCC_MDSS_MDP_CLK 26 +#define DISPCC_MDSS_MDP_CLK_SRC 27 +#define DISPCC_MDSS_MDP_LUT_CLK 28 +#define DISPCC_MDSS_NON_GDSC_AHB_CLK 29 +#define DISPCC_MDSS_PCLK0_CLK 30 +#define DISPCC_MDSS_PCLK0_CLK_SRC 31 +#define DISPCC_MDSS_PCLK1_CLK 32 +#define DISPCC_MDSS_PCLK1_CLK_SRC 33 +#define DISPCC_MDSS_ROT_CLK 34 +#define DISPCC_MDSS_ROT_CLK_SRC 35 +#define DISPCC_MDSS_RSCC_AHB_CLK 36 +#define DISPCC_MDSS_RSCC_VSYNC_CLK 37 +#define DISPCC_MDSS_VSYNC_CLK 38 +#define DISPCC_MDSS_VSYNC_CLK_SRC 39 +#define DISPCC_XO_CLK_SRC 40 +#define DISPCC_SLEEP_CLK 41 +#define DISPCC_SLEEP_CLK_SRC 42 + +/* DISPCC GDSCR */ +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm7150-videocc.h b/include/dt-bindings/clock/qcom,sm7150-videocc.h new file mode 100644 index 000000000000..d86e0fbb159a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7150-videocc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEOCC_SM7150_H +#define _DT_BINDINGS_CLK_QCOM_VIDEOCC_SM7150_H + +#define VIDEOCC_PLL0 0 +#define VIDEOCC_IRIS_AHB_CLK 1 +#define VIDEOCC_IRIS_CLK_SRC 2 +#define VIDEOCC_MVS0_AXI_CLK 3 +#define VIDEOCC_MVS0_CORE_CLK 4 +#define VIDEOCC_MVS1_AXI_CLK 5 +#define VIDEOCC_MVS1_CORE_CLK 6 +#define VIDEOCC_MVSC_CORE_CLK 7 +#define VIDEOCC_MVSC_CTL_AXI_CLK 8 +#define VIDEOCC_VENUS_AHB_CLK 9 +#define VIDEOCC_XO_CLK 10 +#define VIDEOCC_XO_CLK_SRC 11 + +/* VIDEOCC GDSCRs */ +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 +#define VCODEC1_GDSC 2 + +#endif diff --git a/include/dt-bindings/clock/r8a7779-clock.h b/include/dt-bindings/clock/r8a7779-clock.h index 342a60b11934..e39acdc6499c 100644 --- a/include/dt-bindings/clock/r8a7779-clock.h +++ b/include/dt-bindings/clock/r8a7779-clock.h @@ -57,5 +57,4 @@ #define R8A7779_CLK_MMC1 30 #define R8A7779_CLK_MMC0 31 - #endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */ diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h deleted file mode 100644 index c92ff1e60223..000000000000 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ -#define __DT_BINDINGS_CLOCK_R8A7790_H__ - -/* CPG */ -#define R8A7790_CLK_MAIN 0 -#define R8A7790_CLK_PLL0 1 -#define R8A7790_CLK_PLL1 2 -#define R8A7790_CLK_PLL3 3 -#define R8A7790_CLK_LB 4 -#define R8A7790_CLK_QSPI 5 -#define R8A7790_CLK_SDH 6 -#define R8A7790_CLK_SD0 7 -#define R8A7790_CLK_SD1 8 -#define R8A7790_CLK_Z 9 -#define R8A7790_CLK_RCAN 10 -#define R8A7790_CLK_ADSP 11 - -/* MSTP0 */ -#define R8A7790_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7790_CLK_VCP1 0 -#define R8A7790_CLK_VCP0 1 -#define R8A7790_CLK_VPC1 2 -#define R8A7790_CLK_VPC0 3 -#define R8A7790_CLK_JPU 6 -#define R8A7790_CLK_SSP1 9 -#define R8A7790_CLK_TMU1 11 -#define R8A7790_CLK_3DG 12 -#define R8A7790_CLK_2DDMAC 15 -#define R8A7790_CLK_FDP1_2 17 -#define R8A7790_CLK_FDP1_1 18 -#define R8A7790_CLK_FDP1_0 19 -#define R8A7790_CLK_TMU3 21 -#define R8A7790_CLK_TMU2 22 -#define R8A7790_CLK_CMT0 24 -#define R8A7790_CLK_TMU0 25 -#define R8A7790_CLK_VSP1_DU1 27 -#define R8A7790_CLK_VSP1_DU0 28 -#define R8A7790_CLK_VSP1_R 30 -#define R8A7790_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7790_CLK_SCIFA2 2 -#define R8A7790_CLK_SCIFA1 3 -#define R8A7790_CLK_SCIFA0 4 -#define R8A7790_CLK_MSIOF2 5 -#define R8A7790_CLK_SCIFB0 6 -#define R8A7790_CLK_SCIFB1 7 -#define R8A7790_CLK_MSIOF1 8 -#define R8A7790_CLK_MSIOF3 15 -#define R8A7790_CLK_SCIFB2 16 -#define R8A7790_CLK_SYS_DMAC1 18 -#define R8A7790_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7790_CLK_IIC2 0 -#define R8A7790_CLK_TPU0 4 -#define R8A7790_CLK_MMCIF1 5 -#define R8A7790_CLK_SCIF2 10 -#define R8A7790_CLK_SDHI3 11 -#define R8A7790_CLK_SDHI2 12 -#define R8A7790_CLK_SDHI1 13 -#define R8A7790_CLK_SDHI0 14 -#define R8A7790_CLK_MMCIF0 15 -#define R8A7790_CLK_IIC0 18 -#define R8A7790_CLK_PCIEC 19 -#define R8A7790_CLK_IIC1 23 -#define R8A7790_CLK_SSUSB 28 -#define R8A7790_CLK_CMT1 29 -#define R8A7790_CLK_USBDMAC0 30 -#define R8A7790_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7790_CLK_IRQC 7 -#define R8A7790_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7790_CLK_AUDIO_DMAC1 1 -#define R8A7790_CLK_AUDIO_DMAC0 2 -#define R8A7790_CLK_ADSP_MOD 6 -#define R8A7790_CLK_THERMAL 22 -#define R8A7790_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7790_CLK_EHCI 3 -#define R8A7790_CLK_HSUSB 4 -#define R8A7790_CLK_HSCIF1 16 -#define R8A7790_CLK_HSCIF0 17 -#define R8A7790_CLK_SCIF1 20 -#define R8A7790_CLK_SCIF0 21 -#define R8A7790_CLK_DU2 22 -#define R8A7790_CLK_DU1 23 -#define R8A7790_CLK_DU0 24 -#define R8A7790_CLK_LVDS1 25 -#define R8A7790_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7790_CLK_MLB 2 -#define R8A7790_CLK_VIN3 8 -#define R8A7790_CLK_VIN2 9 -#define R8A7790_CLK_VIN1 10 -#define R8A7790_CLK_VIN0 11 -#define R8A7790_CLK_ETHERAVB 12 -#define R8A7790_CLK_ETHER 13 -#define R8A7790_CLK_SATA1 14 -#define R8A7790_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7790_CLK_GPIO5 7 -#define R8A7790_CLK_GPIO4 8 -#define R8A7790_CLK_GPIO3 9 -#define R8A7790_CLK_GPIO2 10 -#define R8A7790_CLK_GPIO1 11 -#define R8A7790_CLK_GPIO0 12 -#define R8A7790_CLK_RCAN1 15 -#define R8A7790_CLK_RCAN0 16 -#define R8A7790_CLK_QSPI_MOD 17 -#define R8A7790_CLK_IICDVFS 26 -#define R8A7790_CLK_I2C3 28 -#define R8A7790_CLK_I2C2 29 -#define R8A7790_CLK_I2C1 30 -#define R8A7790_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7790_CLK_SSI_ALL 5 -#define R8A7790_CLK_SSI9 6 -#define R8A7790_CLK_SSI8 7 -#define R8A7790_CLK_SSI7 8 -#define R8A7790_CLK_SSI6 9 -#define R8A7790_CLK_SSI5 10 -#define R8A7790_CLK_SSI4 11 -#define R8A7790_CLK_SSI3 12 -#define R8A7790_CLK_SSI2 13 -#define R8A7790_CLK_SSI1 14 -#define R8A7790_CLK_SSI0 15 -#define R8A7790_CLK_SCU_ALL 17 -#define R8A7790_CLK_SCU_DVC1 18 -#define R8A7790_CLK_SCU_DVC0 19 -#define R8A7790_CLK_SCU_CTU1_MIX1 20 -#define R8A7790_CLK_SCU_CTU0_MIX0 21 -#define R8A7790_CLK_SCU_SRC9 22 -#define R8A7790_CLK_SCU_SRC8 23 -#define R8A7790_CLK_SCU_SRC7 24 -#define R8A7790_CLK_SCU_SRC6 25 -#define R8A7790_CLK_SCU_SRC5 26 -#define R8A7790_CLK_SCU_SRC4 27 -#define R8A7790_CLK_SCU_SRC3 28 -#define R8A7790_CLK_SCU_SRC2 29 -#define R8A7790_CLK_SCU_SRC1 30 -#define R8A7790_CLK_SCU_SRC0 31 - -#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h deleted file mode 100644 index bb4f18b1b3d5..000000000000 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ -#define __DT_BINDINGS_CLOCK_R8A7791_H__ - -/* CPG */ -#define R8A7791_CLK_MAIN 0 -#define R8A7791_CLK_PLL0 1 -#define R8A7791_CLK_PLL1 2 -#define R8A7791_CLK_PLL3 3 -#define R8A7791_CLK_LB 4 -#define R8A7791_CLK_QSPI 5 -#define R8A7791_CLK_SDH 6 -#define R8A7791_CLK_SD0 7 -#define R8A7791_CLK_Z 8 -#define R8A7791_CLK_RCAN 9 -#define R8A7791_CLK_ADSP 10 - -/* MSTP0 */ -#define R8A7791_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7791_CLK_VCP0 1 -#define R8A7791_CLK_VPC0 3 -#define R8A7791_CLK_JPU 6 -#define R8A7791_CLK_SSP1 9 -#define R8A7791_CLK_TMU1 11 -#define R8A7791_CLK_3DG 12 -#define R8A7791_CLK_2DDMAC 15 -#define R8A7791_CLK_FDP1_1 18 -#define R8A7791_CLK_FDP1_0 19 -#define R8A7791_CLK_TMU3 21 -#define R8A7791_CLK_TMU2 22 -#define R8A7791_CLK_CMT0 24 -#define R8A7791_CLK_TMU0 25 -#define R8A7791_CLK_VSP1_DU1 27 -#define R8A7791_CLK_VSP1_DU0 28 -#define R8A7791_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7791_CLK_SCIFA2 2 -#define R8A7791_CLK_SCIFA1 3 -#define R8A7791_CLK_SCIFA0 4 -#define R8A7791_CLK_MSIOF2 5 -#define R8A7791_CLK_SCIFB0 6 -#define R8A7791_CLK_SCIFB1 7 -#define R8A7791_CLK_MSIOF1 8 -#define R8A7791_CLK_SCIFB2 16 -#define R8A7791_CLK_SYS_DMAC1 18 -#define R8A7791_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7791_CLK_TPU0 4 -#define R8A7791_CLK_SDHI2 11 -#define R8A7791_CLK_SDHI1 12 -#define R8A7791_CLK_SDHI0 14 -#define R8A7791_CLK_MMCIF0 15 -#define R8A7791_CLK_IIC0 18 -#define R8A7791_CLK_PCIEC 19 -#define R8A7791_CLK_IIC1 23 -#define R8A7791_CLK_SSUSB 28 -#define R8A7791_CLK_CMT1 29 -#define R8A7791_CLK_USBDMAC0 30 -#define R8A7791_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7791_CLK_IRQC 7 -#define R8A7791_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7791_CLK_AUDIO_DMAC1 1 -#define R8A7791_CLK_AUDIO_DMAC0 2 -#define R8A7791_CLK_ADSP_MOD 6 -#define R8A7791_CLK_THERMAL 22 -#define R8A7791_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7791_CLK_EHCI 3 -#define R8A7791_CLK_HSUSB 4 -#define R8A7791_CLK_HSCIF2 13 -#define R8A7791_CLK_SCIF5 14 -#define R8A7791_CLK_SCIF4 15 -#define R8A7791_CLK_HSCIF1 16 -#define R8A7791_CLK_HSCIF0 17 -#define R8A7791_CLK_SCIF3 18 -#define R8A7791_CLK_SCIF2 19 -#define R8A7791_CLK_SCIF1 20 -#define R8A7791_CLK_SCIF0 21 -#define R8A7791_CLK_DU1 23 -#define R8A7791_CLK_DU0 24 -#define R8A7791_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7791_CLK_IPMMU_SGX 0 -#define R8A7791_CLK_MLB 2 -#define R8A7791_CLK_VIN2 9 -#define R8A7791_CLK_VIN1 10 -#define R8A7791_CLK_VIN0 11 -#define R8A7791_CLK_ETHERAVB 12 -#define R8A7791_CLK_ETHER 13 -#define R8A7791_CLK_SATA1 14 -#define R8A7791_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7791_CLK_GYROADC 1 -#define R8A7791_CLK_GPIO7 4 -#define R8A7791_CLK_GPIO6 5 -#define R8A7791_CLK_GPIO5 7 -#define R8A7791_CLK_GPIO4 8 -#define R8A7791_CLK_GPIO3 9 -#define R8A7791_CLK_GPIO2 10 -#define R8A7791_CLK_GPIO1 11 -#define R8A7791_CLK_GPIO0 12 -#define R8A7791_CLK_RCAN1 15 -#define R8A7791_CLK_RCAN0 16 -#define R8A7791_CLK_QSPI_MOD 17 -#define R8A7791_CLK_I2C5 25 -#define R8A7791_CLK_IICDVFS 26 -#define R8A7791_CLK_I2C4 27 -#define R8A7791_CLK_I2C3 28 -#define R8A7791_CLK_I2C2 29 -#define R8A7791_CLK_I2C1 30 -#define R8A7791_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7791_CLK_SSI_ALL 5 -#define R8A7791_CLK_SSI9 6 -#define R8A7791_CLK_SSI8 7 -#define R8A7791_CLK_SSI7 8 -#define R8A7791_CLK_SSI6 9 -#define R8A7791_CLK_SSI5 10 -#define R8A7791_CLK_SSI4 11 -#define R8A7791_CLK_SSI3 12 -#define R8A7791_CLK_SSI2 13 -#define R8A7791_CLK_SSI1 14 -#define R8A7791_CLK_SSI0 15 -#define R8A7791_CLK_SCU_ALL 17 -#define R8A7791_CLK_SCU_DVC1 18 -#define R8A7791_CLK_SCU_DVC0 19 -#define R8A7791_CLK_SCU_CTU1_MIX1 20 -#define R8A7791_CLK_SCU_CTU0_MIX0 21 -#define R8A7791_CLK_SCU_SRC9 22 -#define R8A7791_CLK_SCU_SRC8 23 -#define R8A7791_CLK_SCU_SRC7 24 -#define R8A7791_CLK_SCU_SRC6 25 -#define R8A7791_CLK_SCU_SRC5 26 -#define R8A7791_CLK_SCU_SRC4 27 -#define R8A7791_CLK_SCU_SRC3 28 -#define R8A7791_CLK_SCU_SRC2 29 -#define R8A7791_CLK_SCU_SRC1 30 -#define R8A7791_CLK_SCU_SRC0 31 - -/* MSTP11 */ -#define R8A7791_CLK_SCIFA3 6 -#define R8A7791_CLK_SCIFA4 7 -#define R8A7791_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h deleted file mode 100644 index 2948d9ce3a14..000000000000 --- a/include/dt-bindings/clock/r8a7792-clock.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ -#define __DT_BINDINGS_CLOCK_R8A7792_H__ - -/* CPG */ -#define R8A7792_CLK_MAIN 0 -#define R8A7792_CLK_PLL0 1 -#define R8A7792_CLK_PLL1 2 -#define R8A7792_CLK_PLL3 3 -#define R8A7792_CLK_LB 4 -#define R8A7792_CLK_QSPI 5 - -/* MSTP0 */ -#define R8A7792_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7792_CLK_JPU 6 -#define R8A7792_CLK_TMU1 11 -#define R8A7792_CLK_TMU3 21 -#define R8A7792_CLK_TMU2 22 -#define R8A7792_CLK_CMT0 24 -#define R8A7792_CLK_TMU0 25 -#define R8A7792_CLK_VSP1DU1 27 -#define R8A7792_CLK_VSP1DU0 28 -#define R8A7792_CLK_VSP1_SY 31 - -/* MSTP2 */ -#define R8A7792_CLK_MSIOF1 8 -#define R8A7792_CLK_SYS_DMAC1 18 -#define R8A7792_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7792_CLK_TPU0 4 -#define R8A7792_CLK_SDHI0 14 -#define R8A7792_CLK_CMT1 29 - -/* MSTP4 */ -#define R8A7792_CLK_IRQC 7 -#define R8A7792_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7792_CLK_AUDIO_DMAC0 2 -#define R8A7792_CLK_THERMAL 22 -#define R8A7792_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7792_CLK_HSCIF1 16 -#define R8A7792_CLK_HSCIF0 17 -#define R8A7792_CLK_SCIF3 18 -#define R8A7792_CLK_SCIF2 19 -#define R8A7792_CLK_SCIF1 20 -#define R8A7792_CLK_SCIF0 21 -#define R8A7792_CLK_DU1 23 -#define R8A7792_CLK_DU0 24 - -/* MSTP8 */ -#define R8A7792_CLK_VIN5 4 -#define R8A7792_CLK_VIN4 5 -#define R8A7792_CLK_VIN3 8 -#define R8A7792_CLK_VIN2 9 -#define R8A7792_CLK_VIN1 10 -#define R8A7792_CLK_VIN0 11 -#define R8A7792_CLK_ETHERAVB 12 - -/* MSTP9 */ -#define R8A7792_CLK_GPIO7 4 -#define R8A7792_CLK_GPIO6 5 -#define R8A7792_CLK_GPIO5 7 -#define R8A7792_CLK_GPIO4 8 -#define R8A7792_CLK_GPIO3 9 -#define R8A7792_CLK_GPIO2 10 -#define R8A7792_CLK_GPIO1 11 -#define R8A7792_CLK_GPIO0 12 -#define R8A7792_CLK_GPIO11 13 -#define R8A7792_CLK_GPIO10 14 -#define R8A7792_CLK_CAN1 15 -#define R8A7792_CLK_CAN0 16 -#define R8A7792_CLK_QSPI_MOD 17 -#define R8A7792_CLK_GPIO9 19 -#define R8A7792_CLK_GPIO8 21 -#define R8A7792_CLK_I2C5 25 -#define R8A7792_CLK_IICDVFS 26 -#define R8A7792_CLK_I2C4 27 -#define R8A7792_CLK_I2C3 28 -#define R8A7792_CLK_I2C2 29 -#define R8A7792_CLK_I2C1 30 -#define R8A7792_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7792_CLK_SSI_ALL 5 -#define R8A7792_CLK_SSI4 11 -#define R8A7792_CLK_SSI3 12 - -#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h deleted file mode 100644 index 49c66d8ed178..000000000000 --- a/include/dt-bindings/clock/r8a7793-clock.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * r8a7793 clock definition - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ -#define __DT_BINDINGS_CLOCK_R8A7793_H__ - -/* CPG */ -#define R8A7793_CLK_MAIN 0 -#define R8A7793_CLK_PLL0 1 -#define R8A7793_CLK_PLL1 2 -#define R8A7793_CLK_PLL3 3 -#define R8A7793_CLK_LB 4 -#define R8A7793_CLK_QSPI 5 -#define R8A7793_CLK_SDH 6 -#define R8A7793_CLK_SD0 7 -#define R8A7793_CLK_Z 8 -#define R8A7793_CLK_RCAN 9 -#define R8A7793_CLK_ADSP 10 - -/* MSTP0 */ -#define R8A7793_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7793_CLK_VCP0 1 -#define R8A7793_CLK_VPC0 3 -#define R8A7793_CLK_SSP1 9 -#define R8A7793_CLK_TMU1 11 -#define R8A7793_CLK_3DG 12 -#define R8A7793_CLK_2DDMAC 15 -#define R8A7793_CLK_FDP1_1 18 -#define R8A7793_CLK_FDP1_0 19 -#define R8A7793_CLK_TMU3 21 -#define R8A7793_CLK_TMU2 22 -#define R8A7793_CLK_CMT0 24 -#define R8A7793_CLK_TMU0 25 -#define R8A7793_CLK_VSP1_DU1 27 -#define R8A7793_CLK_VSP1_DU0 28 -#define R8A7793_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7793_CLK_SCIFA2 2 -#define R8A7793_CLK_SCIFA1 3 -#define R8A7793_CLK_SCIFA0 4 -#define R8A7793_CLK_MSIOF2 5 -#define R8A7793_CLK_SCIFB0 6 -#define R8A7793_CLK_SCIFB1 7 -#define R8A7793_CLK_MSIOF1 8 -#define R8A7793_CLK_SCIFB2 16 -#define R8A7793_CLK_SYS_DMAC1 18 -#define R8A7793_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7793_CLK_TPU0 4 -#define R8A7793_CLK_SDHI2 11 -#define R8A7793_CLK_SDHI1 12 -#define R8A7793_CLK_SDHI0 14 -#define R8A7793_CLK_MMCIF0 15 -#define R8A7793_CLK_IIC0 18 -#define R8A7793_CLK_PCIEC 19 -#define R8A7793_CLK_IIC1 23 -#define R8A7793_CLK_SSUSB 28 -#define R8A7793_CLK_CMT1 29 -#define R8A7793_CLK_USBDMAC0 30 -#define R8A7793_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7793_CLK_IRQC 7 -#define R8A7793_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7793_CLK_AUDIO_DMAC1 1 -#define R8A7793_CLK_AUDIO_DMAC0 2 -#define R8A7793_CLK_ADSP_MOD 6 -#define R8A7793_CLK_THERMAL 22 -#define R8A7793_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7793_CLK_EHCI 3 -#define R8A7793_CLK_HSUSB 4 -#define R8A7793_CLK_HSCIF2 13 -#define R8A7793_CLK_SCIF5 14 -#define R8A7793_CLK_SCIF4 15 -#define R8A7793_CLK_HSCIF1 16 -#define R8A7793_CLK_HSCIF0 17 -#define R8A7793_CLK_SCIF3 18 -#define R8A7793_CLK_SCIF2 19 -#define R8A7793_CLK_SCIF1 20 -#define R8A7793_CLK_SCIF0 21 -#define R8A7793_CLK_DU1 23 -#define R8A7793_CLK_DU0 24 -#define R8A7793_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7793_CLK_IPMMU_SGX 0 -#define R8A7793_CLK_VIN2 9 -#define R8A7793_CLK_VIN1 10 -#define R8A7793_CLK_VIN0 11 -#define R8A7793_CLK_ETHER 13 -#define R8A7793_CLK_SATA1 14 -#define R8A7793_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7793_CLK_GPIO7 4 -#define R8A7793_CLK_GPIO6 5 -#define R8A7793_CLK_GPIO5 7 -#define R8A7793_CLK_GPIO4 8 -#define R8A7793_CLK_GPIO3 9 -#define R8A7793_CLK_GPIO2 10 -#define R8A7793_CLK_GPIO1 11 -#define R8A7793_CLK_GPIO0 12 -#define R8A7793_CLK_RCAN1 15 -#define R8A7793_CLK_RCAN0 16 -#define R8A7793_CLK_QSPI_MOD 17 -#define R8A7793_CLK_I2C5 25 -#define R8A7793_CLK_IICDVFS 26 -#define R8A7793_CLK_I2C4 27 -#define R8A7793_CLK_I2C3 28 -#define R8A7793_CLK_I2C2 29 -#define R8A7793_CLK_I2C1 30 -#define R8A7793_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7793_CLK_SSI_ALL 5 -#define R8A7793_CLK_SSI9 6 -#define R8A7793_CLK_SSI8 7 -#define R8A7793_CLK_SSI7 8 -#define R8A7793_CLK_SSI6 9 -#define R8A7793_CLK_SSI5 10 -#define R8A7793_CLK_SSI4 11 -#define R8A7793_CLK_SSI3 12 -#define R8A7793_CLK_SSI2 13 -#define R8A7793_CLK_SSI1 14 -#define R8A7793_CLK_SSI0 15 -#define R8A7793_CLK_SCU_ALL 17 -#define R8A7793_CLK_SCU_DVC1 18 -#define R8A7793_CLK_SCU_DVC0 19 -#define R8A7793_CLK_SCU_CTU1_MIX1 20 -#define R8A7793_CLK_SCU_CTU0_MIX0 21 -#define R8A7793_CLK_SCU_SRC9 22 -#define R8A7793_CLK_SCU_SRC8 23 -#define R8A7793_CLK_SCU_SRC7 24 -#define R8A7793_CLK_SCU_SRC6 25 -#define R8A7793_CLK_SCU_SRC5 26 -#define R8A7793_CLK_SCU_SRC4 27 -#define R8A7793_CLK_SCU_SRC3 28 -#define R8A7793_CLK_SCU_SRC2 29 -#define R8A7793_CLK_SCU_SRC1 30 -#define R8A7793_CLK_SCU_SRC0 31 - -/* MSTP11 */ -#define R8A7793_CLK_SCIFA3 6 -#define R8A7793_CLK_SCIFA4 7 -#define R8A7793_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h deleted file mode 100644 index 649f005782d0..000000000000 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ -#define __DT_BINDINGS_CLOCK_R8A7794_H__ - -/* CPG */ -#define R8A7794_CLK_MAIN 0 -#define R8A7794_CLK_PLL0 1 -#define R8A7794_CLK_PLL1 2 -#define R8A7794_CLK_PLL3 3 -#define R8A7794_CLK_LB 4 -#define R8A7794_CLK_QSPI 5 -#define R8A7794_CLK_SDH 6 -#define R8A7794_CLK_SD0 7 -#define R8A7794_CLK_RCAN 8 - -/* MSTP0 */ -#define R8A7794_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7794_CLK_VCP0 1 -#define R8A7794_CLK_VPC0 3 -#define R8A7794_CLK_TMU1 11 -#define R8A7794_CLK_3DG 12 -#define R8A7794_CLK_2DDMAC 15 -#define R8A7794_CLK_FDP1_0 19 -#define R8A7794_CLK_TMU3 21 -#define R8A7794_CLK_TMU2 22 -#define R8A7794_CLK_CMT0 24 -#define R8A7794_CLK_TMU0 25 -#define R8A7794_CLK_VSP1_DU0 28 -#define R8A7794_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7794_CLK_SCIFA2 2 -#define R8A7794_CLK_SCIFA1 3 -#define R8A7794_CLK_SCIFA0 4 -#define R8A7794_CLK_MSIOF2 5 -#define R8A7794_CLK_SCIFB0 6 -#define R8A7794_CLK_SCIFB1 7 -#define R8A7794_CLK_MSIOF1 8 -#define R8A7794_CLK_SCIFB2 16 -#define R8A7794_CLK_SYS_DMAC1 18 -#define R8A7794_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7794_CLK_SDHI2 11 -#define R8A7794_CLK_SDHI1 12 -#define R8A7794_CLK_SDHI0 14 -#define R8A7794_CLK_MMCIF0 15 -#define R8A7794_CLK_IIC0 18 -#define R8A7794_CLK_IIC1 23 -#define R8A7794_CLK_CMT1 29 -#define R8A7794_CLK_USBDMAC0 30 -#define R8A7794_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7794_CLK_IRQC 7 -#define R8A7794_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7794_CLK_AUDIO_DMAC0 2 -#define R8A7794_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7794_CLK_EHCI 3 -#define R8A7794_CLK_HSUSB 4 -#define R8A7794_CLK_HSCIF2 13 -#define R8A7794_CLK_SCIF5 14 -#define R8A7794_CLK_SCIF4 15 -#define R8A7794_CLK_HSCIF1 16 -#define R8A7794_CLK_HSCIF0 17 -#define R8A7794_CLK_SCIF3 18 -#define R8A7794_CLK_SCIF2 19 -#define R8A7794_CLK_SCIF1 20 -#define R8A7794_CLK_SCIF0 21 -#define R8A7794_CLK_DU1 23 -#define R8A7794_CLK_DU0 24 - -/* MSTP8 */ -#define R8A7794_CLK_VIN1 10 -#define R8A7794_CLK_VIN0 11 -#define R8A7794_CLK_ETHERAVB 12 -#define R8A7794_CLK_ETHER 13 - -/* MSTP9 */ -#define R8A7794_CLK_GPIO6 5 -#define R8A7794_CLK_GPIO5 7 -#define R8A7794_CLK_GPIO4 8 -#define R8A7794_CLK_GPIO3 9 -#define R8A7794_CLK_GPIO2 10 -#define R8A7794_CLK_GPIO1 11 -#define R8A7794_CLK_GPIO0 12 -#define R8A7794_CLK_RCAN1 15 -#define R8A7794_CLK_RCAN0 16 -#define R8A7794_CLK_QSPI_MOD 17 -#define R8A7794_CLK_I2C5 25 -#define R8A7794_CLK_I2C4 27 -#define R8A7794_CLK_I2C3 28 -#define R8A7794_CLK_I2C2 29 -#define R8A7794_CLK_I2C1 30 -#define R8A7794_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7794_CLK_SSI_ALL 5 -#define R8A7794_CLK_SSI9 6 -#define R8A7794_CLK_SSI8 7 -#define R8A7794_CLK_SSI7 8 -#define R8A7794_CLK_SSI6 9 -#define R8A7794_CLK_SSI5 10 -#define R8A7794_CLK_SSI4 11 -#define R8A7794_CLK_SSI3 12 -#define R8A7794_CLK_SSI2 13 -#define R8A7794_CLK_SSI1 14 -#define R8A7794_CLK_SSI0 15 -#define R8A7794_CLK_SCU_ALL 17 -#define R8A7794_CLK_SCU_DVC1 18 -#define R8A7794_CLK_SCU_DVC0 19 -#define R8A7794_CLK_SCU_CTU1_MIX1 20 -#define R8A7794_CLK_SCU_CTU0_MIX0 21 -#define R8A7794_CLK_SCU_SRC6 25 -#define R8A7794_CLK_SCU_SRC5 26 -#define R8A7794_CLK_SCU_SRC4 27 -#define R8A7794_CLK_SCU_SRC3 28 -#define R8A7794_CLK_SCU_SRC2 29 -#define R8A7794_CLK_SCU_SRC1 30 - -/* MSTP11 */ -#define R8A7794_CLK_SCIFA3 6 -#define R8A7794_CLK_SCIFA4 7 -#define R8A7794_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index 1be455ba4985..b609fcf96508 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -144,8 +144,7 @@ #define HCLK_TSP 475 #define HCLK_CRYPTO 476 #define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) +#define HCLK_SFC 479 /* soft-reset indices */ #define SRST_CORE0_PO 0 diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index afad90680fce..01e14ab252a7 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -132,8 +132,6 @@ #define HCLK_VDPU 472 #define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_HDMI + 1) - /* soft-reset indices */ #define SRST_MCORE 2 #define SRST_CORE0 3 diff --git a/include/dt-bindings/clock/sophgo,sg2042-clkgen.h b/include/dt-bindings/clock/sophgo,sg2042-clkgen.h new file mode 100644 index 000000000000..84f7857317a2 --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2042-clkgen.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ + +#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0 +#define DIV_CLK_MPLL_AXI_DDR_0 1 +#define DIV_CLK_FPLL_DDR01_1 2 +#define DIV_CLK_FPLL_DDR23_1 3 +#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4 +#define DIV_CLK_FPLL_50M_A53 5 +#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6 +#define DIV_CLK_FPLL_UART_500M 7 +#define DIV_CLK_FPLL_AHB_LPC 8 +#define DIV_CLK_FPLL_EFUSE 9 +#define DIV_CLK_FPLL_TX_ETH0 10 +#define DIV_CLK_FPLL_PTP_REF_I_ETH0 11 +#define DIV_CLK_FPLL_REF_ETH0 12 +#define DIV_CLK_FPLL_EMMC 13 +#define DIV_CLK_FPLL_SD 14 +#define DIV_CLK_FPLL_TOP_AXI0 15 +#define DIV_CLK_FPLL_TOP_AXI_HSPERI 16 +#define DIV_CLK_FPLL_AXI_DDR_1 17 +#define DIV_CLK_FPLL_DIV_TIMER1 18 +#define DIV_CLK_FPLL_DIV_TIMER2 19 +#define DIV_CLK_FPLL_DIV_TIMER3 20 +#define DIV_CLK_FPLL_DIV_TIMER4 21 +#define DIV_CLK_FPLL_DIV_TIMER5 22 +#define DIV_CLK_FPLL_DIV_TIMER6 23 +#define DIV_CLK_FPLL_DIV_TIMER7 24 +#define DIV_CLK_FPLL_DIV_TIMER8 25 +#define DIV_CLK_FPLL_100K_EMMC 26 +#define DIV_CLK_FPLL_100K_SD 27 +#define DIV_CLK_FPLL_GPIO_DB 28 +#define DIV_CLK_DPLL0_DDR01_0 29 +#define DIV_CLK_DPLL1_DDR23_0 30 + +#define GATE_CLK_RP_CPU_NORMAL_DIV0 31 +#define GATE_CLK_AXI_DDR_DIV0 32 + +#define GATE_CLK_RP_CPU_NORMAL_DIV1 33 +#define GATE_CLK_A53_50M 34 +#define GATE_CLK_TOP_RP_CMN_DIV2 35 +#define GATE_CLK_HSDMA 36 +#define GATE_CLK_EMMC_100M 37 +#define GATE_CLK_SD_100M 38 +#define GATE_CLK_TX_ETH0 39 +#define GATE_CLK_PTP_REF_I_ETH0 40 +#define GATE_CLK_REF_ETH0 41 +#define GATE_CLK_UART_500M 42 +#define GATE_CLK_EFUSE 43 + +#define GATE_CLK_AHB_LPC 44 +#define GATE_CLK_AHB_ROM 45 +#define GATE_CLK_AHB_SF 46 + +#define GATE_CLK_APB_UART 47 +#define GATE_CLK_APB_TIMER 48 +#define GATE_CLK_APB_EFUSE 49 +#define GATE_CLK_APB_GPIO 50 +#define GATE_CLK_APB_GPIO_INTR 51 +#define GATE_CLK_APB_SPI 52 +#define GATE_CLK_APB_I2C 53 +#define GATE_CLK_APB_WDT 54 +#define GATE_CLK_APB_PWM 55 +#define GATE_CLK_APB_RTC 56 + +#define GATE_CLK_AXI_PCIE0 57 +#define GATE_CLK_AXI_PCIE1 58 +#define GATE_CLK_SYSDMA_AXI 59 +#define GATE_CLK_AXI_DBG_I2C 60 +#define GATE_CLK_AXI_SRAM 61 +#define GATE_CLK_AXI_ETH0 62 +#define GATE_CLK_AXI_EMMC 63 +#define GATE_CLK_AXI_SD 64 +#define GATE_CLK_TOP_AXI0 65 +#define GATE_CLK_TOP_AXI_HSPERI 66 + +#define GATE_CLK_TIMER1 67 +#define GATE_CLK_TIMER2 68 +#define GATE_CLK_TIMER3 69 +#define GATE_CLK_TIMER4 70 +#define GATE_CLK_TIMER5 71 +#define GATE_CLK_TIMER6 72 +#define GATE_CLK_TIMER7 73 +#define GATE_CLK_TIMER8 74 +#define GATE_CLK_100K_EMMC 75 +#define GATE_CLK_100K_SD 76 +#define GATE_CLK_GPIO_DB 77 + +#define GATE_CLK_AXI_DDR_DIV1 78 +#define GATE_CLK_DDR01_DIV1 79 +#define GATE_CLK_DDR23_DIV1 80 + +#define GATE_CLK_DDR01_DIV0 81 +#define GATE_CLK_DDR23_DIV0 82 + +#define GATE_CLK_DDR01 83 +#define GATE_CLK_DDR23 84 +#define GATE_CLK_RP_CPU_NORMAL 85 +#define GATE_CLK_AXI_DDR 86 + +#define MUX_CLK_DDR01 87 +#define MUX_CLK_DDR23 88 +#define MUX_CLK_RP_CPU_NORMAL 89 +#define MUX_CLK_AXI_DDR 90 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ */ diff --git a/include/dt-bindings/clock/sophgo,sg2042-pll.h b/include/dt-bindings/clock/sophgo,sg2042-pll.h new file mode 100644 index 000000000000..2d519b3bf51c --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2042-pll.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ + +#define MPLL_CLK 0 +#define FPLL_CLK 1 +#define DPLL0_CLK 2 +#define DPLL1_CLK 3 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */ diff --git a/include/dt-bindings/clock/sophgo,sg2042-rpgate.h b/include/dt-bindings/clock/sophgo,sg2042-rpgate.h new file mode 100644 index 000000000000..8b4522d5f559 --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2042-rpgate.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__ + +#define GATE_CLK_RXU0 0 +#define GATE_CLK_RXU1 1 +#define GATE_CLK_RXU2 2 +#define GATE_CLK_RXU3 3 +#define GATE_CLK_RXU4 4 +#define GATE_CLK_RXU5 5 +#define GATE_CLK_RXU6 6 +#define GATE_CLK_RXU7 7 +#define GATE_CLK_RXU8 8 +#define GATE_CLK_RXU9 9 +#define GATE_CLK_RXU10 10 +#define GATE_CLK_RXU11 11 +#define GATE_CLK_RXU12 12 +#define GATE_CLK_RXU13 13 +#define GATE_CLK_RXU14 14 +#define GATE_CLK_RXU15 15 +#define GATE_CLK_RXU16 16 +#define GATE_CLK_RXU17 17 +#define GATE_CLK_RXU18 18 +#define GATE_CLK_RXU19 19 +#define GATE_CLK_RXU20 20 +#define GATE_CLK_RXU21 21 +#define GATE_CLK_RXU22 22 +#define GATE_CLK_RXU23 23 +#define GATE_CLK_RXU24 24 +#define GATE_CLK_RXU25 25 +#define GATE_CLK_RXU26 26 +#define GATE_CLK_RXU27 27 +#define GATE_CLK_RXU28 28 +#define GATE_CLK_RXU29 29 +#define GATE_CLK_RXU30 30 +#define GATE_CLK_RXU31 31 +#define GATE_CLK_MP0 32 +#define GATE_CLK_MP1 33 +#define GATE_CLK_MP2 34 +#define GATE_CLK_MP3 35 +#define GATE_CLK_MP4 36 +#define GATE_CLK_MP5 37 +#define GATE_CLK_MP6 38 +#define GATE_CLK_MP7 39 +#define GATE_CLK_MP8 40 +#define GATE_CLK_MP9 41 +#define GATE_CLK_MP10 42 +#define GATE_CLK_MP11 43 +#define GATE_CLK_MP12 44 +#define GATE_CLK_MP13 45 +#define GATE_CLK_MP14 46 +#define GATE_CLK_MP15 47 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__ */ diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h new file mode 100644 index 000000000000..a199784b3512 --- /dev/null +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li <frank.li@vivo.com> + */ + +#ifndef _DT_BINDINGS_CLK_TH1520_H_ +#define _DT_BINDINGS_CLK_TH1520_H_ + +#define CLK_CPU_PLL0 0 +#define CLK_CPU_PLL1 1 +#define CLK_GMAC_PLL 2 +#define CLK_VIDEO_PLL 3 +#define CLK_DPU0_PLL 4 +#define CLK_DPU1_PLL 5 +#define CLK_TEE_PLL 6 +#define CLK_C910_I0 7 +#define CLK_C910 8 +#define CLK_BROM 9 +#define CLK_BMU 10 +#define CLK_AHB2_CPUSYS_HCLK 11 +#define CLK_APB3_CPUSYS_PCLK 12 +#define CLK_AXI4_CPUSYS2_ACLK 13 +#define CLK_AON2CPU_A2X 14 +#define CLK_X2X_CPUSYS 15 +#define CLK_AXI_ACLK 16 +#define CLK_CPU2AON_X2H 17 +#define CLK_PERI_AHB_HCLK 18 +#define CLK_CPU2PERI_X2H 19 +#define CLK_PERI_APB_PCLK 20 +#define CLK_PERI2APB_PCLK 21 +#define CLK_PERISYS_APB1_HCLK 22 +#define CLK_PERISYS_APB2_HCLK 23 +#define CLK_PERISYS_APB3_HCLK 24 +#define CLK_PERISYS_APB4_HCLK 25 +#define CLK_OSC12M 26 +#define CLK_OUT1 27 +#define CLK_OUT2 28 +#define CLK_OUT3 29 +#define CLK_OUT4 30 +#define CLK_APB_PCLK 31 +#define CLK_NPU 32 +#define CLK_NPU_AXI 33 +#define CLK_VI 34 +#define CLK_VI_AHB 35 +#define CLK_VO_AXI 36 +#define CLK_VP_APB 37 +#define CLK_VP_AXI 38 +#define CLK_CPU2VP 39 +#define CLK_VENC 40 +#define CLK_DPU0 41 +#define CLK_DPU1 42 +#define CLK_EMMC_SDIO 43 +#define CLK_GMAC1 44 +#define CLK_PADCTRL1 45 +#define CLK_DSMART 46 +#define CLK_PADCTRL0 47 +#define CLK_GMAC_AXI 48 +#define CLK_GPIO3 49 +#define CLK_GMAC0 50 +#define CLK_PWM 51 +#define CLK_QSPI0 52 +#define CLK_QSPI1 53 +#define CLK_SPI 54 +#define CLK_UART0_PCLK 55 +#define CLK_UART1_PCLK 56 +#define CLK_UART2_PCLK 57 +#define CLK_UART3_PCLK 58 +#define CLK_UART4_PCLK 59 +#define CLK_UART5_PCLK 60 +#define CLK_GPIO0 61 +#define CLK_GPIO1 62 +#define CLK_GPIO2 63 +#define CLK_I2C0 64 +#define CLK_I2C1 65 +#define CLK_I2C2 66 +#define CLK_I2C3 67 +#define CLK_I2C4 68 +#define CLK_I2C5 69 +#define CLK_SPINLOCK 70 +#define CLK_DMA 71 +#define CLK_MBOX0 72 +#define CLK_MBOX1 73 +#define CLK_MBOX2 74 +#define CLK_MBOX3 75 +#define CLK_WDT0 76 +#define CLK_WDT1 77 +#define CLK_TIMER0 78 +#define CLK_TIMER1 79 +#define CLK_SRAM0 80 +#define CLK_SRAM1 81 +#define CLK_SRAM2 82 +#define CLK_SRAM3 83 +#define CLK_PLL_GMAC_100M 84 +#define CLK_UART_SCLK 85 +#endif diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h new file mode 100644 index 000000000000..6544a1790b83 --- /dev/null +++ b/include/dt-bindings/reset/airoha,en7581-reset.h @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ + +/* RST_CTRL2 */ +#define EN7581_XPON_PHY_RST 0 +#define EN7581_CPU_TIMER2_RST 1 +#define EN7581_HSUART_RST 2 +#define EN7581_UART4_RST 3 +#define EN7581_UART5_RST 4 +#define EN7581_I2C2_RST 5 +#define EN7581_XSI_MAC_RST 6 +#define EN7581_XSI_PHY_RST 7 +#define EN7581_NPU_RST 8 +#define EN7581_I2S_RST 9 +#define EN7581_TRNG_RST 10 +#define EN7581_TRNG_MSTART_RST 11 +#define EN7581_DUAL_HSI0_RST 12 +#define EN7581_DUAL_HSI1_RST 13 +#define EN7581_HSI_RST 14 +#define EN7581_DUAL_HSI0_MAC_RST 15 +#define EN7581_DUAL_HSI1_MAC_RST 16 +#define EN7581_HSI_MAC_RST 17 +#define EN7581_WDMA_RST 18 +#define EN7581_WOE0_RST 19 +#define EN7581_WOE1_RST 20 +#define EN7581_HSDMA_RST 21 +#define EN7581_TDMA_RST 22 +#define EN7581_EMMC_RST 23 +#define EN7581_SOE_RST 24 +#define EN7581_PCIE2_RST 25 +#define EN7581_XFP_MAC_RST 26 +#define EN7581_USB_HOST_P1_RST 27 +#define EN7581_USB_HOST_P1_U3_PHY_RST 28 +/* RST_CTRL1 */ +#define EN7581_PCM1_ZSI_ISI_RST 29 +#define EN7581_FE_PDMA_RST 30 +#define EN7581_FE_QDMA_RST 31 +#define EN7581_PCM_SPIWP_RST 32 +#define EN7581_CRYPTO_RST 33 +#define EN7581_TIMER_RST 34 +#define EN7581_PCM1_RST 35 +#define EN7581_UART_RST 36 +#define EN7581_GPIO_RST 37 +#define EN7581_GDMA_RST 38 +#define EN7581_I2C_MASTER_RST 39 +#define EN7581_PCM2_ZSI_ISI_RST 40 +#define EN7581_SFC_RST 41 +#define EN7581_UART2_RST 42 +#define EN7581_GDMP_RST 43 +#define EN7581_FE_RST 44 +#define EN7581_USB_HOST_P0_RST 45 +#define EN7581_GSW_RST 46 +#define EN7581_SFC2_PCM_RST 47 +#define EN7581_PCIE0_RST 48 +#define EN7581_PCIE1_RST 49 +#define EN7581_CPU_TIMER_RST 50 +#define EN7581_PCIE_HB_RST 51 +#define EN7581_XPON_MAC_RST 52 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */ diff --git a/include/dt-bindings/reset/qcom,qca8k-nsscc.h b/include/dt-bindings/reset/qcom,qca8k-nsscc.h new file mode 100644 index 000000000000..c71167a3bd41 --- /dev/null +++ b/include/dt-bindings/reset/qcom,qca8k-nsscc.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H +#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H + +#define NSS_CC_SWITCH_CORE_ARES 1 +#define NSS_CC_APB_BRIDGE_ARES 2 +#define NSS_CC_MAC0_TX_ARES 3 +#define NSS_CC_MAC0_TX_SRDS1_ARES 4 +#define NSS_CC_MAC0_RX_ARES 5 +#define NSS_CC_MAC0_RX_SRDS1_ARES 6 +#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7 +#define NSS_CC_MAC1_TX_ARES 8 +#define NSS_CC_MAC1_GEPHY0_TX_ARES 9 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10 +#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11 +#define NSS_CC_MAC1_RX_ARES 12 +#define NSS_CC_MAC1_GEPHY0_RX_ARES 13 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14 +#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15 +#define NSS_CC_MAC2_TX_ARES 16 +#define NSS_CC_MAC2_GEPHY1_TX_ARES 17 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18 +#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19 +#define NSS_CC_MAC2_RX_ARES 20 +#define NSS_CC_MAC2_GEPHY1_RX_ARES 21 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22 +#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23 +#define NSS_CC_MAC3_TX_ARES 24 +#define NSS_CC_MAC3_GEPHY2_TX_ARES 25 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26 +#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27 +#define NSS_CC_MAC3_RX_ARES 28 +#define NSS_CC_MAC3_GEPHY2_RX_ARES 29 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30 +#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31 +#define NSS_CC_MAC4_TX_ARES 32 +#define NSS_CC_MAC4_GEPHY3_TX_ARES 33 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34 +#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35 +#define NSS_CC_MAC4_RX_ARES 36 +#define NSS_CC_MAC4_GEPHY3_RX_ARES 37 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38 +#define NSS_CC_MAC5_TX_ARES 39 +#define NSS_CC_MAC5_TX_SRDS0_ARES 40 +#define NSS_CC_MAC5_RX_ARES 41 +#define NSS_CC_MAC5_RX_SRDS0_ARES 42 +#define NSS_CC_AHB_ARES 43 +#define NSS_CC_SEC_CTRL_AHB_ARES 44 +#define NSS_CC_TLMM_ARES 45 +#define NSS_CC_TLMM_AHB_ARES 46 +#define NSS_CC_CNOC_AHB_ARES 47 +#define NSS_CC_MDIO_AHB_ARES 48 +#define NSS_CC_MDIO_MASTER_AHB_ARES 49 +#define NSS_CC_SRDS0_SYS_ARES 50 +#define NSS_CC_SRDS1_SYS_ARES 51 +#define NSS_CC_GEPHY0_SYS_ARES 52 +#define NSS_CC_GEPHY1_SYS_ARES 53 +#define NSS_CC_GEPHY2_SYS_ARES 54 +#define NSS_CC_GEPHY3_SYS_ARES 55 +#define NSS_CC_SEC_CTRL_ARES 56 +#define NSS_CC_SEC_CTRL_SENSE_ARES 57 +#define NSS_CC_SLEEP_ARES 58 +#define NSS_CC_DEBUG_ARES 59 +#define NSS_CC_GEPHY0_ARES 60 +#define NSS_CC_GEPHY1_ARES 61 +#define NSS_CC_GEPHY2_ARES 62 +#define NSS_CC_GEPHY3_ARES 63 +#define NSS_CC_DSP_ARES 64 +#define NSS_CC_GEPHY_FULL_ARES 65 +#define NSS_CC_GLOBAL_ARES 66 +#define NSS_CC_XPCS_ARES 67 +#endif diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h index 0cd80112bea5..9bcee3e9c56c 100644 --- a/include/linux/interconnect-clk.h +++ b/include/linux/interconnect-clk.h @@ -11,12 +11,16 @@ struct device; struct icc_clk_data { struct clk *clk; const char *name; + unsigned int master_id; + unsigned int slave_id; }; struct icc_provider *icc_clk_register(struct device *dev, unsigned int first_id, unsigned int num_clocks, const struct icc_clk_data *data); +int devm_icc_clk_register(struct device *dev, unsigned int first_id, + unsigned int num_clocks, const struct icc_clk_data *data); void icc_clk_unregister(struct icc_provider *provider); #endif |