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2022-05-06arm64: dts: renesas: Remove empty lvds endpointsLaurent Pinchart
Endpoints node must have a remote-endpoint property, as endpoints only exist to model a link between ports. Drop the empty lvds endpoints from SoC dtsi files, they should be instead declared in the board dts or in overlays. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20220424161228.8147-1-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: rzg2ul-smarc: Enable USB2.0 supportBiju Das
Enable USB2.0 Host/Device support on RZ/G2UL SMARC EVK by adding usb{0,1} pincontrol entries to the soc-pinctrl dtsi and deleting the nodes which disabled it. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220429072400.23729-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: rzg2ul-smarc: Enable AudioBiju Das
Enable Audio on RZ/G2UL SMARC EVK by adding ssi1 pincontrol entries to the soc-pinctrl dtsi and ssi1 and cpu sound_dai nodes to the board dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220429072400.23729-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: rzg2l-smarc: Move ssi0 and cpu sound_dai nodes from ↵Biju Das
common dtsi On RZ/G2{L,LC} SoM module, the wm8978 audio codec is connected to ssi0, whereas on RZ/G2UL it is connected to ssi1. So move ssi0 and cpu sound_dai nodes from common dtsi to board specific dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220429072400.23729-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: Add Renesas White Hawk boards supportYoshihiro Shimoda
Initial support for the Renesas White Hawk CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220428135058.597586-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: Add Renesas R8A779G0 SoC supportYoshihiro Shimoda
Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-arm-dt-for-v5.19Geert Uytterhoeven
Renesas R-Car V4H DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0) SoC, shared by driver and DT source files.
2022-04-29arm64: dts: renesas: rzg2ul-smarc-som: Enable watchdogBiju Das
Enable watchdog{0,2} interfaces on RZ/G2UL SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-14-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc-som: Enable OSTMBiju Das
Enable OSTM{1, 2} interfaces on RZ/G2UL SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc: Enable CANFDBiju Das
Enable CANFD on RZ/G2UL SMARC platform. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc: Enable i2c{0,1} and wm8978Biju Das
Enable i2c{0,1} on RZ/G2UL SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable wm8978 audio codec. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the WDT{0,2} stub nodesBiju Das
Fillup the WDT{0,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodesBiju Das
Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the CANFD stub nodeBiju Das
Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add USB2.0 supportBiju Das
Add USB2.0 host and device support by filling usb phy control, phy, device and host stub nodes in RZ/G2UL SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 ↵Biju Das
stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add I2C2 node and fillup the I2C{0,1,3} stub ↵Biju Das
nodes Add I2C2 node and fillup the I2C{0,1,3} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28ARM: dts: r9a06g032: Add missing '#power-domain-cells'Herve Codina
Without '#power-domain-cells' property, power-domains cannot be used. This property is noted required in the device-tree binding. Add '#power-domain-cells' as needed. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220422120850.769480-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: clock: Add r8a779g0 CPG Core Clock DefinitionsYoshihiro Shimoda
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220425064201.459633-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: power: Add r8a779g0 SYSC power domain definitionsYoshihiro Shimoda
Add power domain indices for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220425064201.459633-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-19ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer nodeGeert Uytterhoeven
"make dtbs_check": arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt.yaml: timer: compatible: 'oneOf' conditional failed, one must be fixed: ['arm,cortex-a7-timer', 'arm,armv7-timer'] is too long 'arm,cortex-a7-timer' is not one of ['arm,cortex-a15-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv7-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv8-timer'] From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml The Cortex-A7 timer should just declare compatibility with "arm,armv7-timer". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a8e0cf00a983b4c539cdb1cfad5cc6b10b423c5b.1649680220.git.geert+renesas@glider.be
2022-04-19arm64: dts: renesas: r8a779f0: Add GPIO nodesGeert Uytterhoeven
Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that GPIO blocks 4-7 are not added, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7fb68561026fa8bb5d9baf0596560c5c719a38cc.1649086225.git.geert+renesas@glider.be
2022-04-13arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platformBiju Das
Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK. Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0 device selection is based on the SW1[3] switch position. Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1. Set SW1[3] to position ON for selecting Ethernet0. This patch disables Ethernet0 on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platformBiju Das
RZ/G2UL SoM has both 64GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on SW1[2] on SoM module. Set SW1[2] to position OFF for selecting eMMC Set SW1[2] to position ON for selecting microSD This patch enables eMMC on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platformBiju Das
Enable the microSD card slot connected to SDHI1 on the RZ/G2UL SMARC platform by removing the sdhi1 override which disabled it, and by adding the necessary pinmux required for SDHI1. This patch also adds gpios property to vccq_sdhi1 regulator. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Add GbEthernet nodesBiju Das
Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Add SDHI nodesBiju Das
Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pinsBiju Das
Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting the pinctrl-0 and pinctrl-names properties for scif0 node so that we now actually make use of these properties for scif0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub nodeBiju Das
Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVKBiju Das
Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11): - memory - External input clock - CPG - DMA - SCIF It shares the same carrier board with RZ/G2L, but the pin mapping is different. Disable the device nodes which are not tested and delete the corresponding pinctrl definitions. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoCBiju Das
Add initial DTSI for RZ/G2UL SoC. Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share the common dtsi (rz-smarc.dtsi) file. Place holders are added in device nodes to avoid compilation errors for the devices which have not been enabled yet on RZ/G2UL SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13Merge tag 'renesas-r9a07g043-dt-binding-defs-tag' into HEADGeert Uytterhoeven
Renesas RZ/G2UL DT Binding Definitions Clock and reset definitions for the Renesas RZ/G2UL (R9A07G043) SoC, shared by driver and DT source files.
2022-04-13arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from ↵Biju Das
common dtsi On RZ/G2{L,LC} SoM module, gpio for power selection is connected to P39_1 whereas on RZ/G2UL it is connected to P6_1. So move gpios property of vccq_sdhi1 regulator from common dtsi to soc specific dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220401175427.19078-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier boardBiju Das
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board dtsi file and drops deleting pinctl* properties from DTS file. RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220401145702.17954-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: ulcb: Add RPC HyperFlash device nodeGeert Uytterhoeven
Add the RPC HyperFlash device node along with its partitions to the common ULCB board DTS file. Based on a patch in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/61a63e819d4296760ca7ae83ef5226a2c4d7bd93.1648548339.git.geert+renesas@glider.be
2022-04-13arm64: dts: renesas: salvator-common: Add RPC HyperFlash device nodeGeert Uytterhoeven
Add the RPC HyperFlash device node along with its partitions to the common Salvator-X(S) board DTS file. Based on a patch in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cfc6af8a4c42febcc405b7356c38448eec8e29b0.1648548339.git.geert+renesas@glider.be
2022-04-13arm64: dts: renesas: ebisu: Add RPC HyperFlash device nodeGeert Uytterhoeven
Add the RPC HyperFlash device node along with its partitions to the common Ebisu board DTS file. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b14c769f62211b67d90dbd2f127357756e6cb4fa.1648548339.git.geert+renesas@glider.be
2022-04-13arm64: dts: renesas: draak: Add RPC HyperFlash device nodeGeert Uytterhoeven
Add the RPC HyperFlash device node along with its partitions to the common Draak board DTS file. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0f3d3018ecfcdce1bce67708708a6d3a98368b10.1648548339.git.geert+renesas@glider.be
2022-04-13arm64: dts: renesas: rcar-gen3: Add RPC device nodesGeert Uytterhoeven
Add device nodes for the SPI Multi I/O Bus Controllers (RPC-IF) on the various R-Car Gen3 SoCs that do not have support for them yet in their device trees (R-Car H3, M3-W, M3-W+, M3-N, E3, and D3). Based on patches in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3231749c7b63df1a2134daabe66446a3e0e5515b.1648548339.git.geert+renesas@glider.be
2022-04-13arm64: dts: renesas: rcar-gen4: Add interrupt properties to watchdog nodesWolfram Sang
Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220322095512.4707-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2: Add interrupt properties to watchdog nodesWolfram Sang
Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220322095512.4707-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rcar-gen3: Add interrupt properties to watchdog nodesWolfram Sang
Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220322095512.4707-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13ARM: dts: rzg1: Add interrupt properties to watchdog nodesWolfram Sang
Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220322095512.4707-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13ARM: dts: rcar-gen2: Add interrupt properties to watchdog nodesWolfram Sang
Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220322095512.4707-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13dt-bindings: clock: Add R9A07G043 CPG Clock and Reset DefinitionsBiju Das
Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev. 0.51, Nov. 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220402073037.23947-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-11arm64: dts: renesas: spider: Add Ethernet sub-boardGeert Uytterhoeven
Add a DTS file for the Spider Ether TSN sub-board (RTP8A779F0ASKB0ST0S), and include it from the main r8a779f0-spider.dts. For now its contents are limited to the Board ID EEPROM. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/5aa58816182b34d9e5795bc1e22784f4e4879d13.1643898884.git.geert+renesas@glider.be
2022-04-11arm64: dts: renesas: spider-cpu: Add I2C4 and EEPROMsGeert Uytterhoeven
Enable the I2C4 bus on the Falcon CPU board, and describe the I2C EEPROMs present on the Spider CPU and BreakOut boards. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/6d8917e49f83b6a932970ca169100eb086d11f16.1643898884.git.geert+renesas@glider.be
2022-04-11arm64: dts: renesas: r8a779f0: Add I2C nodesGeert Uytterhoeven
Add device nodes for the I2C Bus Interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e1c7fb17801bc82a74aa5364212d02ba51535dd2.1643898884.git.geert+renesas@glider.be
2022-04-04arm64: dts: renesas: r8a77961: Add CAN-FD nodeKoji Matsuoka
Add the device node for the CAN-FD device on R-Car M3-W+. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220319223306.60782-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: falcon: Enable CANFD 0 and 1Ulrich Hecht
Enables confirmed-working CAN interfaces 0 and 1 on the Falcon board. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20220309162609.3726306-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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