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path: root/arch/riscv/kernel/smp.c
AgeCommit message (Expand)Author
2024-09-17RISC-V: Implement kgdb_roundup_cpus() to enable future NMI RoundupJinjie Ruan
2024-08-07RISC-V: Enable IPI CPU BacktraceRyo Takakura
2024-04-29riscv: Use IPIs for remote cache/TLB flushes by defaultSamuel Holland
2024-01-04riscv: Use the same CPU operations for all CPUsSamuel Holland
2023-08-08riscv: Fix CPU feature detection with SMP disabledSamuel Holland
2023-07-04RISC-V: drop error print from riscv_hartid_to_cpuid()Conor Dooley
2023-04-28Merge tag 'smp-core-2023-04-27' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds
2023-04-08RISC-V: Allow marking IPIs as suitable for remote FENCEsAnup Patel
2023-04-08RISC-V: Treat IPIs as normal Linux IRQsAnup Patel
2023-04-08RISC-V: Clear SIP bit only when using SBI IPI operationsAnup Patel
2023-03-24treewide: Trace IPIs sent via smp_send_reschedule()Valentin Schneider
2022-11-29riscv: kexec: Fixup crash_smp_send_stop without multi coresGuo Ren
2022-08-07Merge tag 'mm-nonmm-stable-2022-08-06-2' of git://git.kernel.org/pub/scm/linu...Linus Torvalds
2022-07-29profile: setup_profiling_timer() is moslty not implementedBen Dooks
2022-07-19riscv: smp: Add 64bit hartid support on RV64Sunil V L
2022-01-09RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=nSean Christopherson
2021-10-26irq: riscv: perform irqentry in entry codeMark Rutland
2021-05-01RISC-V: Fix error code returned by riscv_hartid_to_cpuid()Anup Patel
2021-04-26riscv: Constify sbi_ipi_opsJisheng Zhang
2021-04-26riscv: Mark some global variables __ro_after_initJisheng Zhang
2021-03-16riscv: Enable generic clockevent broadcastGuo Ren
2020-08-20RISC-V: Remove CLINT related code from timer and archAnup Patel
2020-08-20RISC-V: Add mechanism to provide custom IPI operationsAnup Patel
2020-07-30riscv: Support irq_work via self IPIsGreentime Hu
2020-06-09RISC-V: self-contained IPI handling routineAnup Patel
2020-05-04RISC-V: Export riscv_cpuid_to_hartid_mask() APIAnup Patel
2020-03-18riscv: fix the IPI missing issue in nommu modeGreentime Hu
2019-11-17riscv: provide native clint access for M-modeChristoph Hellwig
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig
2019-10-28riscv: add missing header file includesPaul Walmsley
2019-09-20RISC-V: Export kernel symbols for kvmAtish Patra
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig
2019-09-05riscv: optimize send_ipi_singleChristoph Hellwig
2019-09-05riscv: cleanup send_ipi_maskChristoph Hellwig
2019-09-05riscv: refactor the IPI codeChristoph Hellwig
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner
2019-05-16riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel
2019-05-16RISC-V: Fix minor checkpatch issues.Atish Patra
2019-04-30RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra
2019-03-04RISC-V: Fixmap support and MM cleanupsPalmer Dabbelt
2019-03-04RISC-V: Allow hartid-to-cpuid function to fail.Atish Patra
2019-03-04RISC-V: Move cpuid to hartid mapping to SMP.Atish Patra
2019-01-07riscv: don't stop itself in smp_send_stopAndreas Schwab
2018-10-22RISC-V: Show IPI statsAnup Patel
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra
2018-10-22RISC-V: Add logical CPU indexing for RISC-VAtish Patra
2018-08-13RISC-V: simplify software interrupt / IPI codeChristoph Hellwig
2017-12-01RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman