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path: root/drivers/clk/renesas
AgeCommit message (Expand)Author
2024-09-21clk: Switch back to struct platform_driver::remove()Uwe Kleine-König
2024-09-21Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-nextStephen Boyd
2024-09-02clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDTLad Prabhakar
2024-09-02clk: renesas: rzv2h: Add support for dynamic switching divider clocksLad Prabhakar
2024-09-02clk: renesas: r9a08g045: Add clocks, resets and power domains for USBClaudiu Beznea
2024-08-20clk: renesas: r8a779h0: Add CANFD clockCong Dang
2024-08-20clk: renesas: Add RZ/V2H(P) CPG driverLad Prabhakar
2024-08-02clk: Use of_property_present()Rob Herring (Arm)
2024-08-02clk: renesas: Add family-specific clock driver for RZ/V2H(P)Lad Prabhakar
2024-08-02clk: renesas: r8a779h0: Add PWM clockCong Dang
2024-07-30clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configsGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Remove unused fixed PLL clock typesGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Remove unused variable PLL2 clock typeGeert Uytterhoeven
2024-07-30clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLsGeert Uytterhoeven
2024-07-30clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLsGeert Uytterhoeven
2024-07-30clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLsGeert Uytterhoeven
2024-07-30clk: renesas: r8a779a0: Use defines for PLL control registersGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLsGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Add support for fixed variable PLLsGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Add support for variable fractional PLLsGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Add support for fractional multiplicationGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Use defines for common CPG registersGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Use FIELD_GET()Geert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Clarify custom PLL clock supportGeert Uytterhoeven
2024-07-30clk: renesas: rcar-gen4: Removed unused SSMODE_* definitionsGeert Uytterhoeven
2024-07-30clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock regi...Lad Prabhakar
2024-07-30clk: renesas: rzg2l-cpg: Use devres API to register clocksLad Prabhakar
2024-07-30clk: renesas: r8a779h0: Initial clock descriptions should be __initconstGeert Uytterhoeven
2024-07-30clk: renesas: r8a779g0: cpg_pll_configs should be __initconstGeert Uytterhoeven
2024-07-30clk: renesas: r8a779f0: cpg_pll_configs should be __initconstGeert Uytterhoeven
2024-07-30clk: renesas: r8a779a0: cpg_pll_configs should be __initconstGeert Uytterhoeven
2024-07-30clk: renesas: r9a08g045: Add DMA clocks and resetsClaudiu Beznea
2024-07-30clk: renesas: r9a07g043: Add LCDC clock and reset entriesBiju Das
2024-07-30clk: renesas: r8a779h0: Add PCIe clockYoshihiro Shimoda
2024-06-27clk: renesas: r9a08g045: Add clock, reset and power domain support for I2CClaudiu Beznea
2024-06-27clk: renesas: r8a779h0: Add Audio clocksKuninori Morimoto
2024-06-27clk: renesas: r9a08g045: Add clock, reset and power domain support for the VB...Claudiu Beznea
2024-06-24clk: renesas: Drop "Renesas" from individual driver descriptionsGeert Uytterhoeven
2024-06-24clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in commentsGeert Uytterhoeven
2024-06-11clk: renesas: r8a779h0: Add VIN clocksNiklas Söderlund
2024-06-07clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlockGeert Uytterhoeven
2024-06-07clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlockGeert Uytterhoeven
2024-06-07clk: renesas: r8a77970: Use common cpg_lockGeert Uytterhoeven
2024-06-03clk: renesas: r8a779h0: Add CSI-2 clocksNiklas Söderlund
2024-06-03clk: renesas: r8a779h0: Add ISPCS clocksNiklas Söderlund
2024-04-25clk: renesas: r9a08g045: Add support for power domainsClaudiu Beznea
2024-04-25clk: renesas: rzg2l: Extend power domain supportClaudiu Beznea
2024-04-25clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INITGeert Uytterhoeven
2024-04-25clk: renesas: r8a7740: Remove unused div4_clk.flags fieldChristophe JAILLET
2024-04-23clk: renesas: r9a07g043: Add clock and reset entry for PLICLad Prabhakar
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