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path: root/drivers/clk/tegra/clk-dfll.c
AgeCommit message (Expand)Author
2023-03-28clk: tegra: Don't warn three times about failure to unregisterUwe Kleine-König
2022-05-06clk: tegra: Update kerneldoc to match prototypesThierry Reding
2022-05-04clk: tegra: Add missing reset deassertionDiogo Ivo
2021-08-29clk: tegra: fix old-style declarationArnd Bergmann
2020-11-20clk: tegra: Do not return 0 on failureNicolin Chen
2020-01-10clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()Sowjanya Komatineni
2019-11-11clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner
2019-03-14Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2019-02-22clk: tegra: dfll: Fix debugfs_simple_attr.cocci warningsYueHaibing
2019-02-06clk: tegra: dfll: round down voltages based on alignmentJoseph Lo
2019-02-06clk: tegra: dfll: support PWM regulator controlJoseph Lo
2018-11-28clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li
2018-10-16clk: tegra: probe deferral error reportingMarcel Ziswiler
2018-06-01clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen
2017-01-30PM / OPP: Update OPP users to put referenceViresh Kumar
2016-04-28clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding
2016-03-02clk: tegra: Remove CLK_IS_ROOTStephen Boyd
2015-10-20Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Michael Turquette
2015-10-20clk: tegra: dfll: Monitor code is DEBUG_FS onlyThierry Reding
2015-09-16clk: tegra: dfll: Properly protect OPP listThierry Reding
2015-09-15clk: tegra: Unlock top rates for Tegra124 DFLL clockMikko Perttunen
2015-08-25clk: tegra: Fix some static checker problemsStephen Boyd
2015-07-16clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen
2015-07-16clk: tegra: Add closed loop support for the DFLLTuomas Tynkkynen
2015-07-16clk: tegra: Add library for the DFLL clock source (open-loop mode)Tuomas Tynkkynen
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