Age | Commit message (Expand) | Author |
2017-04-04 | clk: tegra: Don't reset PLL-CX if it is already enabled | Jon Hunter |
2017-04-04 | clk: tegra: Add missing Tegra210 clocks | Peter De Schrijver |
2017-04-04 | clk: tegra: Propagate clk_out_x rate to parent | Alex Frid |
2017-03-20 | clk: tegra: Fix build warnings on Tegra20/Tegra30 | Thierry Reding |
2017-03-20 | clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on | Peter De Schrijver |
2017-03-20 | clk: tegra: Add SATA seq input control | Peter De Schrijver |
2017-03-20 | clk: tegra: Add Tegra210 special resets | Peter De Schrijver |
2017-03-20 | clk: tegra: Rework pll_u | Peter De Schrijver |
2017-03-20 | clk: tegra: Implement reset control reset | Mikko Perttunen |
2017-03-20 | clk: tegra: Fix disable unused for clocks sharing enable bit | Peter De Schrijver |
2017-03-20 | clk: tegra: Handle UTMIPLL IDDQ | Peter De Schrijver |
2017-03-20 | clk: tegra: Add aclk | Peter De Schrijver |
2017-03-20 | clk: tegra: Add super clock mux/divider | Peter De Schrijver |
2017-03-20 | clk: tegra: Define Tegra210 DMIC clocks | Peter De Schrijver |
2017-03-20 | clk: tegra: Fix constness for peripheral clocks | Peter De Schrijver |
2017-03-20 | clk: tegra: Define Tegra210 DMIC sync clocks | Peter De Schrijver |
2017-03-20 | clk: tegra: Add CEC clock | Peter De Schrijver |
2017-03-20 | clk: tegra: Fix type for m field | Peter De Schrijver |
2017-03-20 | clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation | Peter De Schrijver |
2017-03-20 | clk: tegra: Don't warn for PLL defaults unnecessarily | Peter De Schrijver |
2017-03-20 | clk: tegra: Remove non-existing pll_m_out1 clock | Peter De Schrijver |
2017-03-20 | clk: tegra: Correct afi clock parent | Peter De Schrijver |
2017-03-20 | clk: tegra: Fix ISP clock modelling | Peter De Schrijver |
2017-03-20 | clk: tegra: Fix pll_a1 iddq register, add pll_a1 | Peter De Schrijver |
2017-02-25 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds |
2017-02-03 | clk: tegra: Add BPMP clock driver | Thierry Reding |
2017-01-30 | PM / OPP: Update OPP users to put reference | Viresh Kumar |
2016-11-10 | clk: tegra: dfll: Use builtin_platform_driver to simplify the code | Wei Yongjun |
2016-11-04 | clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modular | Paul Gortmaker |
2016-11-01 | clk: tegra: dfll: improve function-level documentation | Julia Lawall |
2016-08-24 | clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 | Vince Hsu |
2016-06-30 | clk: tegra: Initialize UTMI PLL when enabling PLLU | Andrew Bresticker |
2016-06-23 | clk: tegra: Micro-optimize Tegra210 clock setup | Thierry Reding |
2016-06-23 | clk: tegra: Make sor_safe the parent of dpaux and dpaux1 | Thierry Reding |
2016-06-22 | clk: tegra: Mark timer clock as critical | Thierry Reding |
2016-06-17 | clk: tegra: Enable sor1 and sor1_src on Tegra210 | Thierry Reding |
2016-06-17 | clk: tegra: Squash sor1 safe/brick/src into a single mux | Thierry Reding |
2016-06-17 | clk: tegra: Disable spread spectrum on pll_d2 | Thierry Reding |
2016-06-10 | clk: tegra: Fixup post dividers on Tegra210 | Thierry Reding |
2016-05-27 | remove lots of IS_ERR_VALUE abuses | Arnd Bergmann |
2016-05-20 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds |
2016-05-18 | Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/a... | Linus Torvalds |
2016-05-09 | Merge tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Arnd Bergmann |
2016-05-02 | Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Stephen Boyd |
2016-04-28 | clk: tegra: dfll: Reformat CVB frequency table | Thierry Reding |
2016-04-28 | clk: tegra: dfll: Properly clean up on failure and removal | Thierry Reding |
2016-04-28 | clk: tegra: dfll: Make code more comprehensible | Thierry Reding |
2016-04-28 | clk: tegra: dfll: Reference CVB table instead of copying data | Thierry Reding |
2016-04-28 | clk: tegra: dfll: Update kerneldoc | Thierry Reding |
2016-04-28 | clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 | Lucas Stach |