summaryrefslogtreecommitdiff
path: root/drivers/cxl/pci.c
AgeCommit message (Expand)Author
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams
2022-05-19cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()Dan Williams
2022-05-19cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams
2022-04-12cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pciDan Williams
2022-04-12cxl/pci: Add debug for DVSEC range init failuresDan Williams
2022-04-12cxl/mbox: Use new return_code handlingDavidlohr Bueso
2022-04-12cxl/mbox: Improve handling of mbox_cmd hw return codesDavidlohr Bueso
2022-04-12cxl/pci: Use CXL_MBOX_SUCCESS to check against mbox_cmd return codeDavidlohr Bueso
2022-04-08cxl/pci: Drop shadowed variableDan Williams
2022-02-08cxl/pci: Emit device serial numberDan Williams
2022-02-08cxl/pci: Implement wait for media activeBen Widawsky
2022-02-08cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky
2022-02-08cxl/pci: Cache device DVSEC offsetBen Widawsky
2022-02-08cxl/pci: Store component register base in cxldsBen Widawsky
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky
2022-02-08cxl: Flesh out register namesBen Widawsky
2022-02-08cxl/pci: Defer mailbox status checks to command timeoutsDan Williams
2022-02-08cxl/pci: Implement Interface Ready TimeoutBen Widawsky
2021-11-15cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny
2021-10-29cxl/pci: Use pci core's DVSEC functionalityBen Widawsky
2021-10-29cxl/pci: Split cxl_pci_setup_regs()Ben Widawsky
2021-10-29cxl/pci: Add @base to cxl_register_mapDan Williams
2021-10-29cxl/pci: Make more use of cxl_register_mapBen Widawsky
2021-10-29cxl/pci: Remove pci request/release regionsBen Widawsky
2021-10-29cxl/pci: Fix NULL vs ERR_PTR confusionDan Williams
2021-10-29cxl/pci: Remove dev_dbg for unknown register blocksBen Widawsky
2021-09-21cxl/pci: Disambiguate cxl_pci further from cxl_memBen Widawsky
2021-09-21cxl/pci: Use module_pci_driverDan Williams
2021-09-21cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the coreDan Williams
2021-09-21cxl/pci: Drop idr.hDan Williams
2021-09-21cxl/mbox: Introduce the mbox_send operationDan Williams
2021-09-21cxl/pci: Clean up cxl_mem_get_partition_info()Dan Williams
2021-09-21cxl/pci: Make 'struct cxl_mem' device type genericDan Williams
2021-09-07cxl/pci: Fix debug message in cxl_probe_regs()Li Qiang (Johnny Li)
2021-09-07cxl/pci: Fix lockdown levelDan Williams
2021-08-10cxl/mem: Adjust ram/pmem range to represent DPA rangesIra Weiny
2021-08-10cxl/mem: Account for partitionable space in ram/pmem rangesIra Weiny
2021-08-07cxl/pci: Store memory capacity valuesIra Weiny
2021-08-06cxl/pci: Simplify register setupBen Widawsky
2021-08-06cxl/pci: Ignore unknown register block typesBen Widawsky
2021-08-06cxl/core: Move memdev management to coreBen Widawsky
2021-08-06cxl/pci: Introduce cdevm_file_operationsDan Williams
2021-08-06cxl: Move cxl_core to new directoryBen Widawsky
2021-06-17cxl/pci: Rename CXL REGLOC IDBen Widawsky
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams
2021-06-14cxl/pci: Add media provisioning required commandsBen Widawsky
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky
2021-06-05cxl/pci: Reserve individual register block regionsIra Weiny
generated by cgit v1.2.3-70-g09d2 (git 2.47.1) at 2024-12-25 08:28:22 +0000