| Age | Commit message (Expand) | Author |
|---|
| 2023-11-09 | drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2) | Victor Lu |
| 2023-11-09 | drm/amdgpu: add pcs xgmi v6.4.0 ras support | Yang Wang |
| 2023-11-09 | drm/amdgpu: Add xcc param to SRIOV kiq write and WREG32_SOC15_IP_NO_KIQ (v4) | Victor Lu |
| 2023-07-18 | drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3) | Victor Lu |
| 2023-06-09 | drm/amdgpu: convert logical instance mask to physical one | Tao Zhou |
| 2023-06-09 | drm/amdgpu: fixes a JPEG get write/read pointer bug | Sonny Jiang |
| 2023-06-09 | drm/amdgpu: add helpers to access registers on different AIDs | Le Ma |
| 2023-06-09 | drm/amdgpu: Use instance lookup table for GC 9.4.3 | Lijo Lazar |
| 2023-06-09 | drm/amdgpu/: add more macro to support offset variant | James Zhu |
| 2023-06-09 | drm/amdgpu: make the WREG32_SOC15_xx macro to support multi GC | Shiwu Zhang |
| 2022-04-28 | drm/amdgpu: add new write field for soc21 | Stanley.Yang |
| 2022-01-25 | drm/amdgpu: switch to amdgpu_sriov_rreg/wreg | Hawking Zhang |
| 2021-12-28 | drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitions | Victor Skvortsov |
| 2021-07-23 | drm/amdgpu: Change the imprecise function name | Roy Sun |
| 2021-06-07 | drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10 | Peng Ju Zhou |
| 2021-06-04 | drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime | shaoyunl |
| 2021-05-21 | drm/amdgpu: Indirect register access for Navi12 sriov | Peng Ju Zhou |
| 2021-04-09 | drm/amdgpu: indirect register access for nv12 sriov | Peng Ju Zhou |
| 2021-03-23 | drm/amdgpu: enable watchdog feature for SQ of aldebaran | Dennis Li |
| 2021-03-23 | drm/amdgpu: add ras support for gfx of aldebaran | Dennis Li |
| 2020-07-01 | drm/amdgpu: fix unused variable | James Zhu |
| 2020-04-24 | drm/amdgpu: provide RREG32_SOC15_NO_KIQ, will be used later | Monk Liu |
| 2020-03-16 | drm/amdgpu: revise RLCG access path | Monk Liu |
| 2019-11-26 | drm/amdgpu: Ensure ret is always initialized when using SOC15_WAIT_ON_RREG | Nathan Chancellor |
| 2019-08-02 | drm/amdgpu: cleanup vega10 SRIOV code path | Monk Liu |
| 2019-05-24 | drm/amdgpu: move the VCN DPG mode read and write to VCN | Leo Liu |
| 2019-05-24 | drm/amdgpu: add basic func for RLC program reg | Trigger Huang |
| 2018-12-18 | drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREG | James Zhu |
| 2018-09-26 | drm/amdgpu/soc15: fix warnings in register macro | Alex Deucher |
| 2018-09-26 | drm/amdgpu:Add DPG mode read/write macro | James Zhu |
| 2018-09-13 | drm/amdgpu:Add error message when register failed to reach expected value | James Zhu |
| 2018-05-24 | drm/amdgpu: Add SOC15_WAIT_ON_RREG macro define | Rex Zhu |
| 2017-12-13 | drm/amdgpu: convert nbio to use callbacks (v2) | Alex Deucher |
| 2017-12-08 | drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset | Shaoyun Liu |
| 2017-12-08 | drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array | Shaoyun Liu |
| 2017-12-08 | drm/amdgpu: Use dynamic IP offset for register access on SOC15 | Shaoyun Liu |
| 2017-07-14 | drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro define | Shaoyun Liu |
| 2017-06-15 | drm/amd/amdgpu: Add offset variant to SOC15 macros | Tom St Denis |
| 2017-04-28 | drm/amd/amdgpu: Introduce new read/write macros for SOC15 | Tom St Denis |
| 2017-03-29 | drm/amdgpu: add common soc15 headers | Ken Wang |
