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path: root/drivers/gpu/drm/amd/display
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2018-07-24drm/amd/display: DC 3.1.58Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24drm/amd/display: separate dc_debug into dc_debug_options and dc_debug dataJun Lei
[why] confusing as to which part of debug is informational, and which part causes behavioral change Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24drm/amd/display: Decouple aux from i2cBhawanpreet Lakha
[Why] Aux engine is created from i2caux layer. We want to remove this layer and use the engine directly. [How] Decouple aux engine from i2caux. Move aux engine related code to dce folder and use dc resource pool to manage the engine. And use the engine functions directly Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24drm/amd/display: DPP CM ICSC AYCRCB8888 format supportvikrant mhaske
[why] Diags has POR to run the video workload using AYCRCB8888 through DCN; capture it through DWB and send it to VCN hardware to encode [how] added the code to support this format so that DPP ICSC will be able to convert it from YUV444 to internal RGB and DWB OCSC will be able to convert from internal RGB to YUV420 Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24drm/amd/display: On dce100, set clocks to 0 on suspendDavid Francis
[Why] When a dce100 asic was suspended, the clocks were not set to 0. Upon resume, the new clock was compared to the existing clock, they were found to be the same, and so the clock was not set. This resulted in a pernicious blackscreen. [How] In atomic commit, check to see if there are any active pipes. If no, set clocks to 0 Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24drm/amd/display: allow diags to skip initial link trainingTony Cheng
[why] diag specify what the full config and is only concerned about pass/fail at the end having inter-op code like verifiying we can actually train at reported link rate slows down diag test and add complexity we don't need [how] add dc_debug option to skip capability link trianing also remove hbr in function name as verify is not specific to hbr Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Ken Chalmers <ken.chalmers@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24drm/amd/display: Remove unnecessary warningMikita Lipski
[why] The warning message floods the dmesg log on Tonga even though it is expected to have a pix_clk set to zero, when the pipe is not active. [how] remove the assert Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-20drm/amd/display: Convert 10kHz clks from PPLib into kHzRex Zhu
Except special naming as *_in_khz, The default clock unit in powerplay is in 10KHz. so need to * 10 as expecting clock frequency in display is in kHz. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-20drm/amd/display: Honor pplib stutter mask for all ASICs in DCHarry Wentland
[Why] We were only setting this mask for DCN, but should really use it universally for all ASICs. [How] Move the assignment out of the Raven switch statement for all ASICs other than Stoney and Carrizo. v2: Keep stutter always on for Carrizo and Stoney (Alex) Cc: Rex.Zhu@amd.com Cc: Feifei.Xu@amd.com Cc: Kenneth.Feng@amd.com Cc: Evan.Quan@amd.com Cc: Bhawanpreet.Lakha@amd.com Cc: Jordan.Lazare@amd.com Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-20drm/amd/display: Drop unused backlight functions in DMHarry Wentland
These are only ever called for non-DC code. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-20Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie
into drm-next More features for 4.19: - Map processes to vmids for debugging GPUVM faults - Raven gfxoff fixes - Initial gfxoff support for vega12 - Use defines for interrupt sources rather than magic numbers - DC aux fixes - Finish DC logging TODO - Add more DC debugfs interfaces for conformance testing - Add CRC support for DCN - Scheduler rework in preparation for load balancing - Unify common smu9 code - Clean up UVD instancing support - ttm cleanups - Misc fixes and cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180719194001.3488-1-alexander.deucher@amd.com
2018-07-20Merge tag 'drm-misc-next-2018-07-18' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 4.19: Core Changes: - add support for DisplayPort CEC-Tunneling-over-AUX (Hans Verkuil) - more doc updates (Daniel Vetter) - fourcc: Add is_yuv field to drm_format_info (Ayan Kumar Halder) - dma-buf: correctly place BUG_ON (Michel Dänzer) Driver Changes: - more vkms support(Rodrigo Siqueira) - many fixes and small improments to all drivers Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180718200826.GA20165@juma
2018-07-19drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86Michel Dänzer
Allowing CONFIG_DRM_AMD_DC_DCN1_0 to be disabled on X86 was an opportunity for display with Raven Ridge accidentally not working. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-17drm/amd/display: Fix DP HBR2 Eye Diagram Pattern on CarrizoHersen Wu
[why] dp hbr2 eye diagram pattern for raven asic is not stabled. workaround is to use tp4 pattern. But this should not be applied to asic before raven. [how] add new bool varilable in asic caps. for raven asic, use the workaround. for carrizo, vega, do not use workaround. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: Fix some checkpatch.pl errors and warnings in dc_link_dp.cHarry Wentland
[Why] Any Linux kernel code should pass checkpatch.pl with no errors and little, if any, warning. [How] Fixing some spacing errors and warnings. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: Null ptr check for set_sdr_white_levelKrunoslav Kovac
[Why&How] Cursor boosting can only be done on DCN+ Check for nullptr since DCE doesn't implement it. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: dal 3.1.56Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: add new dc debug structure to track debug dataJun Lei
[why] Some DTN tests still failing @ 2% Need to reduce. [how] add instrumentation code to driver so we can get more information from failed runs. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: Move address tracking out of HUBPTony Cheng
[Why] We sometime require remapping of FB address space to UMA [How] Move address tracking up a layer before we apply address translation Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: Add hook for MST root branch infoNikola Cornij
This allows DM to do any necessary updates before MST discovery starts. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: add HDR visual confirmGloria Li
[Why] Testing team wants a way to tell if HDR is on or not [How] Program the overscan color to visually indicate the HDR state of the top-most plane Signed-off-by: Gloria Li <geling.li@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: Refactor SDR cursor boosting in HDR modeKrunoslav Kovac
[Why] Cursor boosting is done via CNVC_CUR register which is DPP, not HUBP Previous commit was implementing it in HUBP functions, and also breaking diags tests. [How] 1. Undo original commit as well as Eric's diags test fix, almost completely 2. Move programming to DPP and call via new dc_stream function 3. Also removing cur_rom_en from dpp_cursor_attributes and programming as part of normal cursor attributes as it depends on cursor color format Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amd/display: Add headers for hardcoded 1d luts.Vitaly Prosyak
Hard-coded luts are needed since complex algorithms are used for color and tone mapping. Add the headers for future use. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: properly turn autocal offDmytro Laktyushkin
[why] Currently we do not turn off autocal when scaling is in bypass. In case vbios enalbes auto scale and our first mode set is a non-scaled mode we have autocal on causing screen corruption. [how] moves turning autocal off to be first thing done during scaler setup Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Initialize data structure for DalMpVisualConfirm.Hugo Hu
[Why] Prevent unexpected color shows if DalMpVisualConfirm enable. [How] Zero out color configuration data for DalMpVisualConfirm when initiating. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: dal 3.1.55Tony Cheng
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: update dml to match DV dmlDmytro Laktyushkin
DV updated their dml with an option to use max vstartup, this updates dc dml with the same option Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: add max scl ratio to soc bounding boxDmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Fix new stream count check in dc_add_stream_to_ctxKen Chalmers
[Why] The previous code could allow through attempts to enable more streams than there are timing generators, in designs where the number of pipes is greater than the number of timing generators. [How] Compare the new stream count to the resource pool's timing generator count, instead of its pipe count. Also correct a typo in the error message. Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: dp debugfs allow link rate lane count greater than dp rx ↵Hersen Wu
reported caps [Why] when hw team does phy parameters tuning, there is need to force dp link rate or lane count grater than the values from dp receiver to check dp tx. current debufs limit link rate, lane count no more than rx caps. [How] remove force settings less than rx caps check v2: Fix typo in title Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Expose couple OPTC functions through headerDavid Francis
Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Add CRC support for DCNDavid Francis
[Why] Regamma/CTM tests require CRC support [How] The CRC registers that were used in DCE exist under different names in DCN. The code was copied from DCE (in dc/dce110/dce110_timing_generator.c) into DCN, and changed to use the DCN register access helper functions. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Return out_link_loss from interrupt handlerFatemeh Darbehani
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Add NULL check for local sink in edp_power_controlYue Hin Lau
[WHY] PNP cause bsod regression fix [HOW] Add NULL check Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Hugo Hu <Hugo.Hu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: add pp to dc powerlevel enum translatorMikita Lipski
[why] Add a switch statement to translate pp's powerlevel enum to dc powerlevel statement enum [how] Add a translator function Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: add DalEnableHDMI20 key supportCharlene Liu
[why] "DalEnableHDMI20" set to 0, disallow HDMI YCbCr420 and pixel clock > 340Mhz Default is enabled. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: introduce concept of send_reset_length for i2c enginesCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Read AUX channel even if only status byte is returnedLeo (Sunpeng) Li
[Why] get_channel_status() can return 0 in returned_bytes, and report a successful operation result. This is because it prunes the first status byte out. This was preventing read_channel_reply() from being called (due to the faulty condition), and consequently preventing the AUX reply status from being set. [How] Fix the conditional so that it accounts for when get_channel_status() returns 0 bytes read. [Fixes] Fixes possible edid read failures during S3 resume, where we are now relying on DRM's DP AUX handling. This was an regression introduced by: Author: Harry Wentland <harry.wentland@amd.com> drm/amd/display: Return aux replies directly to DRM Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Right shift AUX reply value sooner than laterLeo (Sunpeng) Li
[Why] There is no point in keeping the AUX reply value in the raw format as returned from reading the AUX_SW_DATA register. [How] Shift it within read_channel_reply(), where the register is read, before returning it. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Expose bunch of functions from dcn10_hw_sequencerEric Bernstein
v2: Remove spurious newline changes Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Add YCbCr420 only support for HDMI 4K@60Jerry (Fangzhi) Zuo
[Why] Some monitors mark 4K@60 capable HDMI port only have 300MHz TMDS maximum, but the edid includes 4K@60 mode in cea extension block. [How] To enable 4K@60, need to limit BW by allowing YCbCr420 ONLY mode. Add YCbCr420 only support for monitors that do not fully support HDMI2.0, e.g., ASUS PA328. The YCbCr420 only support applies to DCN, DCE112 or higher. Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: dal 3.1.54Tony Cheng
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Linux hook test pattern through debufsHersen Wu
bug fix: phy test PLTAT is special 80bit test pattern. The 80bit data should be hard coded within driver so that user does not need input the deata. previous driver does not have hard coded 80 bits pattern data for PLTPAT. Other than this PLTPAT, user has to input 80 bits pattern data. In case user input less than 10 bytes data, un-input data byte will be filled by 0x00. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: expose dcn10_aux_initialize in headerYongqiang Sun
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: add dcn cursor hotsport rotation and mirror supportDmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: set default GPIO_ID_HPDCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: add missing mask for dcnCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Duke Du <Duke.Du@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Fix compile error on older GCC versionsLeo (Sunpeng) Li
GCC 4.9 reports a 'missing braces around initializer' error. This is a bug, documented here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119 Fix it by adding another brace. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Linux set/read lane settings through debugfsHersen Wu
function: get current DP PHY settings: voltage swing, pre-emphasis, post-cursor2 (defined by VESA DP specification) valid values: voltage swing: 0,1,2,3 pre-emphasis : 0,1,2,3 post cursor2 : 0,1,2,3 debugfs file phy_setings is located at /sys/kernel/debug/dri/0/DP-x there will be directories, like DP-1, DP-2,DP-3, etc. for DP display --- to figure out which DP-x is the display for DP to be check, cd DP-x ls -ll There should be debugfs file, like link_settings, phy_settings. cat link_settings from lane_count, link_rate to figure which DP-x is for display to be worked on --- to get current DP PHY settings, cat phy_settings --- to change DP PHY settings, echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 0, echo 2 3 0 > phy_settings --- to check if change be applied, get current phy settings by cat phy_settings --- in case invalid values are set by user, like echo 1 4 0 > phy_settings HW will NOT be programmed by these settings. cat phy_settings will show the previous valid settings. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/display: Patch for extend time to panel poweron.Hugo Hu
[WHY] In eDP spec, the min duration in LCDVDD on-off-on sequence should be 500ms, some BOE panels need 700ms to pass. [HOW] Add patch to wait more time when eDP power on. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3-70-g09d2 (git 2.51.0) at 2025-09-26 05:36:06 +0000