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path: root/drivers/gpu/drm/amd/display
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2018-12-18drm/amd/display: Don't skip link training for empty dongleEric Yang
[Why] Skipping initial link training will result in no verified link cap for mode enumeration. Some versions of the BIOS seem to have PHY programming sequence issue as well if initial link training is skipped, resulting in a softlock in BIOS command table. [How] Identify the empty dongle hotplug case, and still do initial link training. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: Wait edp HPD to high in detect_sinkDale Zhao
[Why] In 99% user case, edp will be post by vbios. In 1% / current case: Lenovo don't light up edp panel in vbios post stage, vbios won't be lit up. Thus in dal when we init DCN 10 hw, we power up edp, then we start detect_sink, but internal time is too short, when we detect it, HPD is still low, so we don't detect the edp, and edp shows black. [How] When we init hw, we wait edp HPD to high after power up edp. Signed-off-by: Dale Zhao <dale.zhao@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: fix surface update sequenceDmytro Laktyushkin
An earlier change added update of interdependent dlg/ttu params for pipes not being updated in the current call. The code fails to check if the other pipes are actually active yet causing an assert. This change adds a check for surface presence on the pipes before updating the interdepenednt params. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: fix YCbCr420 blank colorEric Yang
[Why] YCbCr420 packing format uses two chanels for luma, and 1 channel for both chroma component. Our previous implementation did not account for this and results in every other pixel having very high luma value, showing greyish color instead of black. YCbCr444 = <Y1, Cb1, Cr1>; <Y2, Cb2, Cr2> ..... YCbCr420 = <Y1, Y2, Cb1>; <Y3, Y4, Cr1> ..... [How] Program the second channel with the black color value for luma as well. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Hugo Hu <Hugo.Hu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: Warn instead of error on REG_WAIT timeoutDavid Francis
[Why] DC warns when a REG_WAIT takes a while and full-on errors with stack dump on REG_WAIT timeout. Most of the time it isn't a real issue. [How] Make DC cool its jets - taking a while is a debug message (because it is not something that normal users should need to be aware of), and timeouts are warnings (because it technically shouldn't happen, but it's not a big deal if it does) Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: move AYCrCb8888 format to video sectionDmytro Laktyushkin
This is a dual channel format and should be treated like other video formats Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: Don't log error if we have no connectorsHarry Wentland
[Why] In certain configurations, such as PX configs or some Vega20 parts DC gets created without connectors. [How] Drop the dm_error print when no connectors. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: Add functionality to get XGMI SS infoLeo Li
[Why] When XGMI is enabled, the DP reference clock needs to be adjusted according to the XGMI spread spectrum percentage and mode. But first, we need the ability to fetch this info. [How] Within the BIOS parser, Read from vBIOS when XGMI SS info is requested. In addition, diags build uses include_legacy/atomfirmware.h for the smu_info_v3_3 table headers. Update that as well. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: Add DCE_VERSION_12_1 enum for Vega 20Leo Li
[Why] We'll need a way to differentiate Vega 20 in DC [How] Add a DCE_VERSION_12_1 enum, which will be returned as the DC version if the ASIC used is a Vega 20. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: Add below the range support for FreeSyncNicholas Kazlauskas
[Why] When the flip-rate is below the minimum supported variable refresh rate range for the monitor the front porch wait will timeout and be frequently misaligned resulting in stuttering and/or flickering. The FreeSync module can still maintain a smooth and flicker free image when the monitor has a refresh rate range such that the maximum refresh > 2 * minimum refresh by utilizing low framerate compensation, "below the range". [How] Hook up the pre-flip and post-flip handlers from the FreeSync module. These adjust the minimum/maximum vrr range to duplicate frames when appropriate by tracking flip timestamps. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: Raise dispclk value for PolarisRoman Li
[Why] The visual corruption due to low display clock value observed on some systems [How] There was earlier patch for dspclk: 'drm/amd/display: Raise dispclk value for dce_update_clocks' Adding +15% workaround also to to dce112_update_clocks Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Leo Li <Sunpeng.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-18drm/amd/display: Skip fast cursor updates for fb changesNicholas Kazlauskas
[Why] The behavior of drm_atomic_helper_cleanup_planes differs depending on whether the commit was asynchronous or not. When it's called from amdgpu_dm_atomic_commit_tail during a typical atomic commit the plane state has been swapped so it calls cleanup_fb on the old plane state. However, in the asynchronous commit codepath the call to drm_atomic_helper_commit also calls dm_plane_helper_cleanup_fb after atomic_async_update has been called. Since the plane state is updated in place and has not been swapped the cleanup_fb call affects the new plane state. This results in a use after free for the given sequence: - Fast update, fb1 pin/ref, fb1 unpin/unref - Fast update, fb2 pin/ref, fb2 unpin/unref - Slow update, fb1 pin/ref, fb2 unpin/unref - Fast update, fb2 pin/ref -> use after free. bug [How] Disallow framebuffer changes in the fast path. Since this includes a NULL framebuffer, this means that only framebuffers that have been previously pin+ref at least once will be used, preventing a use after free. This has a significant throughput reduction for cursor updates where the framebuffer changes. For most desktop usage this isn't a problem, but it does introduce performance regressions for two specific IGT tests: - cursor-vs-flip-toggle - cursor-vs-flip-varying-size Fixes: 2cc751931afc ("drm/amd/display: Add fast path for cursor plane updates") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-12drm/amd/display: Add fast path for cursor plane updatesNicholas Kazlauskas
[Why] Legacy cursor plane updates from drm helpers go through the full atomic codepath. A high volume of cursor updates through this slow code path can cause subsequent page-flips to skip vblank intervals since each individual update is slow. This problem is particularly noticeable for the compton compositor. [How] A fast path for cursor plane updates is added by using DRM asynchronous commit support provided by async_check and async_update. These don't do a full state/flip_done dependency stall and they don't block other commit work. However, DC still expects itself to be single-threaded for anything that can issue register writes. Screen corruption or hangs can occur if write sequences overlap. Every call that potentially perform register writes needs to be guarded for asynchronous updates to work. The dc_lock mutex was added for this. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106175 Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-11drm/amd/display: Fix duplicating scaling/underscan connector stateNicholas Kazlauskas
[Why] These properties aren't being carried over when the atomic state. This tricks atomic check and commit tail into performing underscan and scaling operations when they aren't needed. With the patch that forced scaling/RMX_ASPECT on by default this results in many unnecessary surface updates and hangs under certain conditions. [How] Duplicate the properties. Fixes: 91b66c47ba34 ("drm/amd/display: Set RMX_ASPECT as default") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-11drm/amd/display: Fix unintialized max_bpc state valuesNicholas Kazlauskas
[Why] If the "max bpc" isn't explicitly set in the atomic state then it have a value of 0. This has the correct behavior of limiting a panel to 8bpc in the case where the panel supports 8bpc. In the case of eDP panels this isn't a true assumption - there are panels that can only do 6bpc. Banding occurs for these displays. [How] Initialize the max_bpc when the connector resets to 8bpc. Also carry over the value when the state is duplicated. Bugzilla: https://bugs.freedesktop.org/108825 Fixes: 307638884f72 ("drm/amd/display: Support amdgpu "max bpc" connector property") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-11Revert "drm/amd/display: Set RMX_ASPECT as default"Nicholas Kazlauskas
This reverts commit 91b66c47ba3468f7882ea4a84d5e0e0c186b638f. Forcing RMX_ASPECT as default uses the preferred/native mode's timings for any mode the user selects and scales the image. This provides a a consistently nicer result in the case where the selected mode's refresh rate matches the native mode's refresh but this isn't always the case. For example, if the monitor is 1080p@144Hz and the preferred mode is 60Hz then even if the user selects 1080p@144Hz as their selected mode they'll get 1080p@60Hz. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-10drm/dp-mst-helper: Remove hotplug callbackDaniel Vetter
When everyone implements it exactly the same way, among all 4 implementations, there's not really a need to overwrite this at all. Aside: drm_kms_helper_hotplug_event is pretty much core functionality at this point. Probably should move it there. Reviewed-by: Lyude Paul <lyude@redhat.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128221234.15054-1-daniel.vetter@ffwll.ch
2018-12-05drm/amd/display: Add tracing to dcDavid Francis
[Why] Tracing is a useful and cheap debug functionality [How] This creates a new trace system amdgpu_dm, currently with three trace events amdgpu_dc_rreg and amdgpu_dc_wreg report the address and value of any dc register reads and writes amdgpu_dc_performance requires at least one of those two to be enabled. It counts the register reads and writes since the last entry v2: Don't check for NULL before kfree Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-04drm/amd/display: Fix overflow/truncation from strncpy.Nicholas Kazlauskas
[Why] New GCC warnings for stringop-truncation and stringop-overflow help catch common misuse of strncpy. This patch suppresses these warnings by fixing bugs identified by them. [How] Since the parameter passed for name in amdpgu_dm_create_common_mode has no fixed length, if the string is >= DRM_DISPLAY_MODE_LEN then mode->name will not be null-terminated. The truncation in fill_audio_info won't actually occur (and the string will be null-terminated since the buffer is initialized to zero), but the warning can be suppressed by using the proper buffer size. This patch fixes both issues by using the real size for the buffer and making use of strscpy (which always terminates). Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Clean up for DCN1 clock debug loggingFatemeh Darbehani
[Why] To prepare for clock debug logging. With the exception of removing max_supported_dppclk_khz from logs, there are no functional changes. [How] Add clk_bypass struct and clean up buffer logic Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Su Chung <Su.Chung@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: 3.2.08Steven Chiu
Signed-off-by: Steven Chiu <steven.chiu@amd.com> Reviewed-by: Fatemeh Darbehani <Fatemeh.Darbehani@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Allow clock lower on dce100David Francis
dce100 was set to always pass safe_to_lower = false to the clock manager Thus, on suspend the clocks were not being set to 0 which is incorrect behaviour This was causing s3 resume to blackscreen on intel CPUs with dce100 GPUs attached (Note that the hash in this Fixes: tag is the hash on Alex's tree) Fixes: ae7d8aeb38d7 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead") Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Program dithering if requestedSivapiriyanKumarasamy
Dithering needs to be enabled or disabled as requested. If dc_stream_update->dither_option is non-null, program the FMT blocks. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Copy crc_enabled when duplicating dm_crtc_stateNicholas Kazlauskas
[Why] When running igt@kms_plane@pixel-format-pipe-* tests the CRC read will time out and the test will fail. This is because the CRTC is duplicated but the crc_enabled parameter isn't copied over to the new dm_crtc_state. CRC reads will time out because amdgpu_dm_crtc_handle_crc_irq will no longer call drm_crtc_add_crc_entry. [How] Copy crc_enabled when duplicating the state. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Add customizable tracing eventChiawen Huang
[why] add customizable log with a message input, which is for adding test log in debugging as printf function in ETW. [Usage] EVENT_LOG_CUST_MSG1("TestLog","Hello World %d=0x%x", 123, pDC); Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Re-arrange GFX9 fieldsNevenko Stupar
For more clear usage in future Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: fbc state could not reach while enable fbchersen wu
[WHY] fbc is within the data path from memory to dce. while re-configure mc dmif, fbc should be enabled. otherwise, fbc may not be enabled properly. [HOW] before re-configure mc dmif, disable fbc, only after dmif re-configuration fully done, enable fbc again. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Info frame cleanupHarmanprit Tatla
* Use provided infopacket in stream (if valid) instead of reconstructing in set_vendor_info_packet() * Use proper format for enums * Use dc info packet struct instead Signed-off-by: Harmanprit Tatla <Harmanprit.Tatla@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: CTS 4.2.2.7abdoulaye berthe
[Why] Failure to read Detailed Capabilities Info. [How] Read Detailed Capbilities Info 80h-08Fh. Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Fix spelling of axis in modules/color/color_gamma.cKrunoslav Kovac
Use axis instead of axix Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Remove unused panel patch "disconnect_delay"Joshua Aberback
[Why] This patch is for use by dm, no need for it in dc. Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Start documentation of DCDavid Francis
[Why] There are a lot of unintuitive parts of the dm-dc interface. It would help us if these were documented to provide a common understanding of what they are supposed to do [How] Most of this documentation is stubs, to be filled out more thoroughly by the experts Not every dm-accessible function and struct is mentioned. Simple functions like getters, setters, retain, release, create, destroy can be left unadorned. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: 3.2.07Steven Chiu
Signed-off-by: Steven Chiu <steven.chiu@amd.com> Reviewed-by: Shahin Khayyer <Shahin.Khayyer@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: fix sporadic multiple aux transaction failureYogesh Mohan Marimuthu
[why] When there are multiple aux transaction in parallel, it is sometime sporadically the aux transaction starts to continuously fail. The aux transaction was failing because the busy bit for the given gpio pin was always set. The busy bit was alway set because the programming sequence to read, modify and write busy bit was not atomic. Due to which when multiple threads are trying to modify the busy bits for their gpio pins in the same integer variable sometimes the busy bits integer variable is written with old data causing failure. [how] Instead of using individual bits to track gpio pins and grouping them to integers, one byte will be allcoated for each gpio pin. Now whenever a gpio pin needs to be set to mark being used, only writing a value of one to that byte is sufficient, other bytes are not impacted. Also no need to have atomicity with bytes unlike with bits. Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Fix NULL ptr deref for commit_planes_to_streamNicholas Kazlauskas
[Why] With scaling, underscan and abm changes we can end up calling commit_planes_to_stream in commit_tail. This call uses dm_state->context which can be NULL if the commit was a fast update. [How] Use dc_state instead since that can't be NULL unless the system ran out of memory. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108912 Fixes: e64abff2f133 ("drm/amd/display: Use private obj helpers for dm_atomic_state") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-29drm/amd/display: Fix NULL ptr when calculating refresh rateJerry (Fangzhi) Zuo
Calculate preferred refresh rate only when preferred mode exists. Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-29drm/amd/display: Fix 6x4K displays light-up on Vega20Roman Li
[Why] More than 4x4K didn't lightup on Vega20 due to low dcfclk value. Powerplay expects valid min requirement for dcfclk from DC. [How] Update min_dcfclock_khz based on min_engine_clock value. Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-29drm/amd/display: Fix 6x4K displays light-up on Vega20 (v2)Roman Li
[Why] More than 4x4K didn't lightup on Vega20 due to low dcfclk value. Powerplay expects valid min requirement for dcfclk from DC. [How] Update min_dcfclock_khz based on min_engine_clock value. v2: backport to 4.20 (Alex) Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-29drm/amd/display: Fix unintialized max_bpc state valuesNicholas Kazlauskas
[Why] If the "max bpc" isn't explicitly set in the atomic state then it have a value of 0. This has the correct behavior of limiting a panel to 8bpc in the case where the panel supports 8bpc. In the case of eDP panels this isn't a true assumption - there are panels that can only do 6bpc. Banding occurs for these displays. [How] Initialize the max_bpc when the connector resets to 8bpc. Also carry over the value when the state is duplicated. Bugzilla: https://bugs.freedesktop.org/108825 Fixes: 307638884f72 ("drm/amd/display: Support amdgpu "max bpc" connector property") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-29Merge v4.20-rc4 into drm-nextDave Airlie
Requested by Boris Brezillon for some vc4 fixes that are needed for future vc4 work. Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-11-28drm/amdgpu: Set FreeSync state using drm VRR propertiesNicholas Kazlauskas
Support for AMDGPU specific FreeSync properties and ioctls are dropped from amdgpu_dm in favor of supporting drm variable refresh rate properties. The notify_freesync and set_freesync_property functions are dropped from amdgpu_display_funcs. The drm vrr_capable property is now attached to any DP/HDMI connector. Its value is updated accordingly to the connector's FreeSync capabiltiy. The freesync_enable logic and ioctl control has has been dropped in favor of utilizing the vrr_enabled on the drm CRTC. This allows for more fine grained atomic control over which CRTCs should support variable refresh rate. To handle state changes for vrr_enabled it was easiest to drop the forced modeset on freesync_enabled change. This patch now performs the required stream updates when planes are flipped. This is done for a few reasons: (1) VRR stream updates can be done in the fast update path (2) amdgpu_dm_atomic_check would need to be hacked apart to check desired variable refresh state and capability before the CRTC disable pass. (3) Performing VRR stream updates on-flip is needed for enabling BTR support. VRR packets and timing adjustments are now tracked and compared to previous values sent to the hardware. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-28drm/amd/display: Fix compile error with ACPI disabledDavid Francis
The fallback code for getting default backlight caps was using the wrong variable name. Fix it. Fixes: https://lists.freedesktop.org/archives/dri-devel/2018-November/197752.html Signed-off-by: David Francis <David.Francis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-28drm/amd/display: Use private obj helpers for dm_atomic_stateNicholas Kazlauskas
[Why] Two non-blocking commits in succession can result in a sequence where the same dc->current_state is queried for both commits. 1. 1st commit -> check -> commit -> swaps atomic state -> queues work 2. 2nd commit -> check -> commit -> swaps atomic state -> queues work 3. 1st commit work finishes The issue with this sequence is that the same dc->current_state is read in both atomic checks. If the first commit modifies streams or planes those will be missing from the dc->current_state for the second atomic check. This result in many stream and plane errors in atomic commit tail. [How] The driver still needs to track old to new state to determine if the commit in its current implementation. Updating the dc_state in atomic tail is wrong since the dc_state swap should be happening as part of drm_atomic_helper_swap_state *before* the worker queue kicks its work off. The simplest replacement for the subclassing (which doesn't properly manage the old to new atomic state swap) is to use the drm private object helpers. While some of the dc_state members could be merged into dm_crtc_state or dm_plane_state and copied over that way it is easier for now to just treat the whole dc_state structure as a single private object. This allows amdgpu_dm to drop the dc->current_state copy from within atomic check. It's replaced by a copy from the current atomic state which is propagated correctly for the sequence described above. Since access to the dm_state private object is now locked this should also fix issues that could arise if submitting non-blocking commits from different threads. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-26drm/amd/display: Remove duplicate headerBrajeswar Ghosh
Remove dce/dce_mem_input.h which is included more than once Signed-off-by: Brajeswar Ghosh <brajeswar.linux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-26drm/amd: Query and use ACPI backlight capsDavid Francis
ACPI ATIF has a function called query backlight transfer characteristics. Among the information returned by this function is the minimum and maximum input signals for the backlight Call that function on ACPI init. When DM backlight device is updated, copy over the backlight caps into DM, but only once. Use the backlight caps in the backlight-to-dc calculation Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-26drm/amd: Add abm level drm propertyDavid Francis
Adaptive Backlight Management (ABM) is a feature that reduces backlight level to save power, while increasing pixel contrast and pixel luminance to maintain readability and image quality. ABM will adjust in response to the pixel luminance of the displayed content. ABM is made available as a drm property on eDP monitors called "abm level", which ranges from 0 to 4. When this property is set to 0, ABM is off. Levels 1 to 4 represent different ranges of backlight reduction. At higher levels both the backlight reduction and pixel adjustment will be greater. ABM requires DMCU firmware, which is currently available for Raven ASICs only. If the feature does not work, please ensure your firmware is up to date. v2: Fix commit message, only attach property if DMCU loaded v3: Store ABM level in crtc state to accommodate dc v4: Fix ABM saving on dpms cycle Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-26drm/amd/display: Load DMCU IRAMDavid Francis
DMCU IRAM must be loaded by the driver before DMCU can function. Move the IRAM code out of the shadows and into a new file modules/power/power_helpers.c The IRAM table contains the backlight curve and ABM parameters Add this new file to the Makefiles Call dmcu_load_iram in late init of DM Move struct dmcu_version from dc.h to dmcu.h to allow dmcu to be included on its own Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-26drm/amd/display: Fix Scaling (RMX_*) for DC driverBhawanpreet Lakha
Before: We use drm_match_cea_mode() to get the vic for any mode we want to set, most of the time vic will be different for the new mode. DC uses memcmp to check if timing changed, in this case DC will say timing changed and we endup doing a full modeset. Current: Now we check if !RMX_OFF and old_refresh == new_refresh if so we copy the vic from old timing. In a case where we are currently on a lower timing and want to change to higher mode, stream->dst will be different and cause us to do a full modeset, which is what we want. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-26drm/amd/display: Set RMX_ASPECT as defaultBhawanpreet Lakha
Setting this allows for display scaling by default Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-21drm/amd/dm: Understand why attaching path/tile properties are neededLyude Paul
Path property is used for userspace to know what MST connector goes to what actual DRM DisplayPort connector, the tiling property is for tiling configurations. Not sure what else there is to figure out. Signed-off-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Cc: Stable <stable@vger.kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>