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path: root/drivers/gpu/drm/amd/display
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2020-04-24drm/amd/display: Fix green screen issue after suspendRodrigo Siqueira
[why] We have seen a green screen after resume from suspend in a Raven system connected with two displays (HDMI and DP) on X based system. We noticed that this issue is related to bad DCC metadata from user space which may generate hangs and consequently an underflow on HUBP. After taking a deep look at the code path we realized that after resume we try to restore the commit with the DCC enabled framebuffer but the framebuffer is no longer valid. [how] This problem was only reported on Raven based system and after suspend, for this reason, this commit adds a new parameter on fill_plane_dcc_attributes() to give the option of disabling DCC programmatically. In summary, for disabling DCC we first verify if is a Raven system and if it is in suspend; if both conditions are true we disable DCC temporarily, otherwise, it is enabled. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1099 Co-developed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2020-04-24drm/amd/display: blank dp stream before re-train the linkXiaodong Yan
[Why] When link loss happened, monitor can not light up if only re-train the link. [How] Blank all the DP streams on this link before re-train the link, and then unblank the stream Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-24drm/amd/display: DispalyPort: Write OUI only if panel supports itAurabindo Pillai
[why] Organizational Unit Identifier register is optional, and its presence is published via Down Stream Port Count register. Writing this register when not available will result in errors [how] Read this register and continue writing OUI only if the panel has the support advertised. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-23drm: amd/display: fix Kconfig help textRandy Dunlap
Fix help text: indent one tab + 2 spaces; end a sentence with a period; and collapse short lines of text to one line. Fixes: 23c61b4599c4 ("drm/amd: Fix Kconfig indentation") Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: fix bug in the logic for panel power controlAnthony Koo
[Why] there's a bug in the new logic for panel power control. the check is wrong, and will skip panel power control under the wrong conditions. [How] fix to check for NULL panel_cntl Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Convert memory from cpu to fw endianness correctlyWyatt Wood
[Why] Current code does not guarantee the correct endianness of memory being copied to fw, specifically in the case where cpu isn't little endian. [How] Windows and Diags are always little endian, so we define a macro that does nothing. Linux already defines this macro and will do the correct endianness conversion. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Fix green screen issue after suspendRodrigo Siqueira
[why] We have seen a green screen after resume from suspend in a Raven system connected with two displays (HDMI and DP) on X based system. We noticed that this issue is related to bad DCC metadata from user space which may generate hangs and consequently an underflow on HUBP. After taking a deep look at the code path we realized that after resume we try to restore the commit with the DCC enabled framebuffer but the framebuffer is no longer valid. [how] This problem was only reported on Raven based system and after suspend, for this reason, this commit adds a new parameter on fill_plane_dcc_attributes() to give the option of disabling DCC programmatically. In summary, for disabling DCC we first verify if is a Raven system and if it is in suspend; if both conditions are true we disable DCC temporarily, otherwise, it is enabled. Co-developed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Adjust refactored dm for color management onlyStylon Wang
[Why] Commit cdde482caabf2adad47d23f0d1e235db2c4f2b7d is causing regression from changing the order of call sequence. [How] Keep the call sequence and take in extra dm state only if plane-level color management is enabled. Fixes: cdde482caabf2a ("drm/amd/display: Refactor color management to take dm plane state") Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: access ABM from stream resource.Yongqiang Sun
[Why] Since ABM resource is mapped to stream res, all the ABM access should via stream res. [How] Get ABM instance from stream res instead of resource pool. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: blank dp stream before re-train the linkXiaodong Yan
[Why] When link loss happened, monitor can not light up if only re-train the link. [How] Blank all the DP streams on this link before re-train the link, and then unblank the stream Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: DispalyPort: Write OUI only if panel supports itAurabindo Pillai
[why] Organizational Unit Identifier register is optional, and its presence is published via Down Stream Port Count register. Writing this register when not available will result in errors [how] Read this register and continue writing OUI only if the panel has the support advertised. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: change from panel to panel cntlAnthony Koo
[Why] it doesn't represent panel specifically, it's more like the control logic for the panel [How] change from panel to panel cntl to make it a bit more clear Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Add HW rotation cursor changes to dcn10Jaehyun Chung
[Why] HW rotation was enabled in DAL3 but hubp cursor calculations for HW roation were only added to dcn20. [How] Add hubp cursor position calculation changes to dcn10. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Factor in immediate flip support into DLG calculationsNicholas Kazlauskas
[Why] We expect to be able to perform immediate flipping without having to recalculate and update all the watermarks. There are certain usecases today (1080p @ 90deg, 2160p @ 90deg) such that we get a urgency value of 0 for frac_urg_bw_flip because we're explicitly passing in a value of "false" for requiring immediate flip support into the DLG calculation. [How] Always pass in true into the calculation. With this we get a correct non-zero value for frac_urg_bw_flip. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: fix virtual signal dsc setupDmytro Laktyushkin
This prevents dpcd access on virtual links. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: destroy panel on link destructAnthony Koo
[Why] without destroy it is causing a memory leak [How] destroy panel on link destruct Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: dmcu wait loop calculation is incorrect in RVPaul Hsieh
[Why] Driver already get display clock from SMU base on MHz, but driver read again and mutiple 1000 cause wait loop value is overflow. [How] remove coding error Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: move panel power seq to new panel structAnthony Koo
[Why] panel power sequencer is currently just sitting in hwseq but it really it tied to internal panels [How] make a new panel struct to contain power sequencer code Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: make all backlight calls link basedAnthony Koo
[Why] Backlight adjustment is tied to a specific display. So make the calls target a link rather than making it a global state. [How] make all backlight calls link based Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1Sung Lee
[WHY] In certain conditions with low pixel clock, some values in DML may go past the max due to margining for latency hiding. This causes assertions to get hit. [HOW] If the pixel clock is low and some values are high, cap it to the max. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Various fixes for PSR on DMCUBWyatt Wood
[Why] - Driver does not recognize new definitions of psr states. - Internal tool is required for checking if psr is active. [How] - Parse psr state correctly so that driver will recognize psr state. - Add visual confirmation that psr is active using existing mechanisms. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: 3.2.81Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Update MPCC if requestedAric Cyr
Don't skip MPCC tree updates if requested. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Fix HDR visual confirmAric Cyr
Some cases were incorrectly reporting the wrong visual confirm, even though they were working as expected. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Use the correct input TF for video formatsNicholas Kazlauskas
[Why] Color blending for NV12 formats is incorrect because we're using the predefined SRGB degamma. [How] Calculate the correct input transfer function for degamma from the color module depending on what the actual surface format is. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Zhan Liu <Zhan.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Change infopacket type programmingHaiyi Zhou
[Why] Certain displays may experience blanking if infopacket max range does not equal nominal refresh rate. [How] Add additional infopacket versions to program range to full or forced range in freesync states. This does not change the vrr logic. Signed-off-by: Haiyi Zhou <haiyi.zhou@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Avoid NULL pointer in set_backlight when ABM is NULLNicholas Kazlauskas
[Why] On ASIC without ABM support (most dGPU) we run into a null pointer dereference when attempting to set the backlight level. [How] This function requires ABM, so fix up the condition to only allow DMCU to be optional. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: fix stream setting for diags on siliconDmytro Laktyushkin
We need to set up stream even with virtual displays when running diags. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Cast int to float before divisionSung Lee
[Why]: Some inputs to dml_ceil have it dividied by int which causes a truncation. This loss of precision means the ceil function becomes redundant and does not round up. [How]: Cast parameter to float before division. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Set meta_chunk_value to 0 in DML if DCC disabled in DCN2.1Sung Lee
[WHY]: Calculating refcyc_per_meta_chunk_vblank_l when DCC is disabled may lead to a large number causing an assert to get hit. In VBA, this value is 0 when DCC is disabled. [HOW]: Set value to 0 to avoid hitting the assert. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: add optc get crc support for timings with ODM/DSCWenjing Liu
[why] Optc needs to know if timing is enabled with ODM or DSC before computing crc. Otherwise value computed will be inaccurate. Before this change, the CRC computed without ODM is not equal to the CRC computed with ODM for the same timing. This is unexpected as we are driving the same timing despite of the underlaying hardware setup to achieve it. This is caused by missing hardware programming sequence to support it. [how] Add the new programming sequence based on hardware guide. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Workaround to disable YCbCrJinze Xu
[Why] Some mst dock can't translate DP to HDMI properly. [How] Bypass YCbCr timings on specific MST device. Signed-off-by: Jinze Xu <jinze.xu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Check ramp != NULL before applying lut1d for degammaNicholas Kazlauskas
[Why] A NULL ramp is a valid configuration for passing into mod_color_calculate_degamma_params but we'll hit a NULL pointer if we do so. We need this in order to get the right transfer function to do degamma on NV12 formats where we aren't supplied with a custom user degamma. [How] Add the NULL check. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Zhan Liu <Zhan.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Unify psr feature flagsWyatt Wood
[Why] As it stands, psr has feature flags in dm, stream, and link. Most are not defined well enough, and different dm layers have different uses for these same flags. [How] We define a new structure called psr_settings in dc_link that will hold the following psr feature flags: psr_feature_enable - psr is supported psr_allow_active - psr is currently active psr_version - internal psr version supported psr_frame_capture_indication_req psr_sdp_transmit_line_num_deadline The last two flags were moved out of the power module for the purposes of consolidating psr flags. Their use is already well-defined. Psr caps reported by sink will also be stored in dc_link, in dpcd_caps.psr_caps. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Support plane-level gamut remap in DMStylon Wang
[Why] Plane-level gamut remap is not enabled in DM, which is necessary to support CTM as a plane-level property. [How] Enable gamut remap in DM. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Add SetBacklight call to abm on dmcubWyatt Wood
[Why] Set backlight calls to firmware are are being prevented by dmcu == null check. Dmcu is expected to be null in this case. [How] Only prevent call if dmcu and abm are null. Also rename variable 'use_smooth_brightness' to 'fw_set_brightness' as it's more appropriate. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Remove byte swapping for dmcub abm config tableWyatt Wood
[Why] Since x86 and dmcub are both little endian, byte swapping isn't necessary. Dmcu requires byte swapping as it is big endian. [How] Add flag to function definitions to determine if byte swapping is necessary. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Force watermark value propagationJoshua Aberback
[Why] The HUBBUB watermark registers are in an area that cannot be power gated, but the HUBP copies of the watermark values are in areas that can be power gated. When we power on a pipe, it will not automatically take the HUBBUB values, we need to force propagation by writing to a watermark register. [How] - new HUBBUB function to re-write current value in a WM register - touch WM register after enabling the plane in program_pipe Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Move enable fractional pwm callWyatt Wood
[Why] Dmcu init fw call has some logic to initialize abm values. Since this doesn't exist on dmcub, must find a proper place for it in the abm sequence. [How] Move enable fractional pwm call. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Add user backlight level reg writeWyatt Wood
[Why] Porting abm from dmcu to dmcub missed one register write. [How] Add this register write in the SetBacklightLevel sequence. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Correct updating logic of dcn21's pipe VM flagsDale Zhao
[Why]: Renoir's pipe VM flags are not correctly updated if pipe strategy has changed during some scenarios. It will result in watermarks mistakenly calculation, thus underflow and garbage appear. [How]: Correctly update pipe VM flags to pipes which have been populated. Signed-off-by: Dale Zhao <dale.zhao@amd.com> Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Remove aconnector condition check for dpcd readZhan Liu
[Why] Aconnector is not necessary to be NULL in order to read dpcd successfully. Actually if we rely on checking aconnector here, we won't be able to turn off all displays before doing display detection. That will cause some MST hubs not able to light up. [How] Remove aconnector check when turning off all displays at hardware initialization stage. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Joseph Gravenor <joseph.gravenor@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/dc: remove unused variable 'video_optimized_pixel_rates'YueHaibing
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c:1017:50: warning: ‘video_optimized_pixel_rates’ defined but not used [-Wunused-const-variable=] static const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = { ^~~~~~~~~~~~~~~~~~~~~~~~~~~ commit d8cd587d2bfd ("drm/amd/display: removing MODULO change for dcn2") left behind this unused vairable, remove it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amdgpu/display: give aux i2c buses more meaningful namesAlex Deucher
Mirror what we do for i2c display buses. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amdgpu/display: fix aux registration (v2)Alex Deucher
We were registering the aux device in the MST late_register rather than the regular one. v2: handle eDP as well Fixes: 405a1f9090d1ac ("drm/amdgpu/display: split dp connector registration (v4)") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1100 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
2020-04-22drm/amd/display: remove redundant assignment to variable dp_ref_clk_khzColin Ian King
The variable dp_ref_clk_khz is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22Merge tag 'drm-misc-next-2020-04-14' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.8: UAPI Changes: - drm: error out with EBUSY when device has existing master - drm: rework SET_MASTER and DROP_MASTER perm handling Cross-subsystem Changes: - mm: export two symbols from slub/slob - fbdev: savage: fix -Wextra build warning - video: omap2: Use scnprintf() for avoiding potential buffer overflow Core Changes: - Remove drm_pci.h - drm_pci_{alloc/free)() are now legacy - Introduce managed DRM resourcesA - Allow drivers to subclass struct drm_framebuffer - Introduce struct drm_afbc_framebuffer and helpers - fbdev: remove return value from generic fbdev setup - Introduce simple-encoder helper - vram-helpers: set fence on plane - dp_mst: ACT timeout improvements - dp_mst: Remove drm_dp_mst_has_audio() - TTM: ttm_trace_dma_{map/unmap}() cleanups - dma-buf: add flag for PCIP2P support - EDID: Various improvements - Encoder: cleanup semantics of possible_clones and possible_crtcs - VBLANK documentation updates - Writeback documentation updates Driver Changes: - Convert several drivers to i2c_new_client_device() - Drop explicit drm_mode_config_cleanup() calls from drivers - Auto-release device structures with drmm_add_final_kfree() - Init bfdev console after registering DRM device - Make various .debugfs functions return 0 unconditionally; ignore errors - video: Use scnprintf() to avoid buffer overflows - Convert drivers to simple encoders - drm/amdgpu: note that we can handle peer2peer DMA-buf - drm/amdgpu: add support for exporting VRAM using DMA-buf v3 - drm/kirin: Revert change to register connectors - drm/lima: Add optional devfreq and cooling device support - drm/lima: Various improvements wrt. task handling - drm/panel: nt39016: Support multiple modes and 50Hz - drm/panel: Support Leadtek LTK050H3146W - drm/rockchip: Add support for afbc - drm/virtio: Various cleanups - drm/hisilicon/hibmc: Enforce 128-byte stride alignment - drm/qxl: Fix notify port address of cursor ring buffer - drm/sun4i: Improvements to format handling - drm/bridge: dw-hdmi: Various improvements Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200414090738.GA16827@linux-uq9g
2020-04-17drm/amdgpu/display: give aux i2c buses more meaningful namesAlex Deucher
Mirror what we do for i2c display buses. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-17drm/amdgpu/display: fix aux registration (v2)Alex Deucher
We were registering the aux device in the MST late_register rather than the regular one. v2: handle eDP as well Fixes: 405a1f9090d1ac ("drm/amdgpu/display: split dp connector registration (v4)") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1100 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
2020-04-17Merge tag 'topic/phy-compliance-2020-04-08' of ↵Thomas Zimmermann
git://anongit.freedesktop.org/drm/drm-misc into drm-misc-next Topic pull request for topic/phy-compliance: - Standardize DP_PHY_TEST_PATTERN name. - Add support for setting/getting test pattern from sink. - Implement DP PHY compliance to i915. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> # gpg: Signatur vom Mi 08 Apr 2020 14:46:42 CEST # gpg: mittels RSA-Schlüssel B97BD6A80CAC4981091AE547FE558C72A67013C3 # gpg: Signatur kann nicht geprüft werden: Kein öffentlicher Schlüssel From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/efb3d0d9-2cf7-046b-3a9b-2548d086258e@linux.intel.com
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-08-01 15:05:01 +0000