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path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.c
AgeCommit message (Expand)Author
2024-04-17drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä
2024-03-26drm/i915/de: register wait function renamesJani Nikula
2024-03-21drm/i915/cx0: pass encoder instead of i915 and port aroundJani Nikula
2024-03-21drm/i915/cx0: remove the unused intel_is_c10phy()Jani Nikula
2024-03-21drm/i915/display: use intel_encoder_is/to_* functionsJani Nikula
2024-03-21drm/i915/display: add intel_encoder_is_*() and _to_*() functionsJani Nikula
2024-02-14drm/i915/display: update pll values in sync with Bspec for MTLRavi Kumar Vodapalli
2024-01-30drm/i915/xe2lpd: Move registers to PICALucas De Marchi
2024-01-08drm/i915/display: Use helper to select C20 MPLLA/BMika Kahola
2024-01-04drm/i915/display: Skip C10 state verification in case of fastsetMika Kahola
2024-01-04drm/i915/display: Cleanup mplla/mpllb selectionMika Kahola
2024-01-04drm/i915/display: Store hw clock for C20Mika Kahola
2024-01-04drm/i915/display: Fix C20 pll selection for state verificationMika Kahola
2023-12-15drm/i915/mtl: Fix HDMI/DP PLL clock selectionImre Deak
2023-12-08drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_stateRadhakrishna Sripada
2023-12-08drm/i915/mtl: Remove misleading "clock" field from C20 pll_stateRadhakrishna Sripada
2023-12-08drm/i915/mtl: Use port clock compatible numbers for C20 phyRadhakrishna Sripada
2023-12-01drm/i915/display: Skip state verification with TBT-ALT modeMika Kahola
2023-11-13drm/i915/mtl: C20 state verificationMika Kahola
2023-10-29drm/i915/display: Abstract C10/C20 pll calculationLucas De Marchi
2023-10-29drm/i915/display: Abstract C10/C20 pll hw readoutLucas De Marchi
2023-10-29drm/i915/lnl: Extend C10/C20 phyLucas De Marchi
2023-10-26drm/i915/display: Reset message bus after each read/write operationMika Kahola
2023-10-16drm/i915/display: Clean up zero initializersVille Syrjälä
2023-10-11drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes OwnedKhaled Almahallawy
2023-10-07drm/i915: Simplify snps/c10x DPLL state checker calling convetionVille Syrjälä
2023-10-07drm/i915: Constify the snps/c10x PLL state checkersVille Syrjälä
2023-09-18drm/i915/cx0: Add step for programming msgbus timerGustavo Sousa
2023-09-06drm/i915/cx0: Check and increase msgbus timeout thresholdGustavo Sousa
2023-09-05drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()Luca Coelho
2023-08-21drm/i915/display: Eliminate IS_METEORLAKE checksMatt Roper
2023-08-17drm/i915/cx0: Program vswing only for owned lanesGustavo Sousa
2023-08-17drm/i915/cx0: Enable/disable TX only for owned PHY lanesGustavo Sousa
2023-08-17drm/i915: Simplify intel_cx0_program_phy_lane() with loopGustavo Sousa
2023-08-17drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()Gustavo Sousa
2023-06-20drm/i915/mtl: Fix SSC selection for MPLLARadhakrishna Sripada
2023-06-15drm/i915/mtl: Cleanup usage of phy lane resetMika Kahola
2023-06-05drm/i915/mtl: Reset only one lane in case of MFDMika Kahola
2023-05-19drm/i915/hdmi: C20 computed PLL frequenciesClint Taylor
2023-05-18drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disablingMika Kahola
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula
2023-04-28drm/i915/mtl: Power up TCSSMika Kahola
2023-04-28drm/i915/mtl: Readout Thunderbolt HW stateMika Kahola
2023-04-28drm/i915/mtl: Enabling/disabling sequence Thunderbolt pllMika Kahola
2023-04-28drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLAMika Kahola
2023-04-28drm/i915/mtl: C20 port clock calculationMika Kahola
2023-04-28drm/i915/mtl: Dump C20 pll hw stateMika Kahola
2023-04-28drm/i915/mtl: C20 HW readoutMika Kahola
2023-04-28drm/i915/mtl: C20 PLL programmingMika Kahola
2023-04-15drm/i915: Make intel_{mpllb,c10pll}_state_verify() saferVille Syrjälä
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