summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_ddi.c
AgeCommit message (Expand)Author
2021-02-16drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routingVille Syrjälä
2021-02-16drm/i915: Relocate icl_sanitize_encoder_pll_mapping()Ville Syrjälä
2021-02-16drm/i915: Use .disable_clock() for pll sanitationVille Syrjälä
2021-02-16drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Extract _cnl_ddi_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()Ville Syrjälä
2021-02-16drm/i915: Sprinkle a few missing locks around shared DDI clock registersVille Syrjälä
2021-02-16drm/i915: Use intel_de_rmw() for DDI clock routingVille Syrjälä
2021-02-16drm/i915: Extract icl+ .{enable,disable}_clock() vfuncsVille Syrjälä
2021-02-16drm/i915: Convert DG1 over to .{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i195: Extract cnl_ddi_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Extract skl_ddi_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Extract hsw_ddi_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Introduce .{enable,disable}_clock() encoder vfuncsVille Syrjälä
2021-02-16drm/i915: Use intel_ddi_clk_select() for FDIVille Syrjälä
2021-02-12drm/i915/gen9_bc: Introduce HPD pin mappings for TGP PCH + CML combosLyude Paul
2021-02-11drm/i915/display: Handle lane polarity for DDI portUma Shankar
2021-02-08drm/i915: refactor skylake scaler code into new file.Dave Airlie
2021-02-08drm/i915: migrate skl planes code new file (v5)Dave Airlie
2021-02-05drm/i915: migrate hsw fdi code to new file.Dave Airlie
2021-02-05drm/i915: refactor ddi translations into a separate file (v2)Dave Airlie
2021-02-02Merge tag 'topic/adl-s-enabling-2021-02-01-1' of git://anongit.freedesktop.or...Jani Nikula
2021-01-30drm/i915: Don't check tc_mode unless dealing with a TC PHYVille Syrjälä
2021-01-30drm/i915: Move HDMI vswing programming to the right placeVille Syrjälä
2021-01-30drm/i915: Power up combo PHY lanes for for HDMI as wellVille Syrjälä
2021-01-30drm/i915: Extract intel_ddi_power_up_lanes()Ville Syrjälä
2021-01-30drm/i915: Skip vswing programming for TBTVille Syrjälä
2021-01-26drm/i915/adl_s: Configure Port clock registers for ADL-SAditya Swarup
2021-01-25drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare
2021-01-25drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare
2021-01-25drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare
2021-01-21drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä
2021-01-21drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä
2021-01-19drm/i915: Fix the PHY compliance test vs. hotplug mishapVille Syrjälä
2021-01-14drm/i915/pps: rename intel_edp_panel_* to intel_pps_*Jani Nikula
2021-01-14drm/i915/pps: abstract panel power sequencer from intel_dp.cJani Nikula
2021-01-13drm/i915/hdcp: Encapsulate hdcp_port_data to dig_portAnshuman Gupta
2021-01-13drm/i915/hdcp: HDCP stream encryption supportAnshuman Gupta
2021-01-13drm/i915/hdcp: DP MST transcoder for link and streamAnshuman Gupta
2021-01-11drm/i915/dg1: Update voltage swing tables for DPMatt Roper
2021-01-11drm/i915: Fix HTI port checkingJosé Roberto de Souza
2021-01-08Merge drm/drm-next into drm-intel-nextRodrigo Vivi
2021-01-07Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter
2021-01-06drm/i915/rkl: Add DP vswing programming tablesMatt Roper
2020-12-22drm/i915/display: Let PCON convert from RGB to YCbCr if it canAnkit Nautiyal
2020-12-22drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encodingAnkit Nautiyal
2020-12-22drm/i915: Check for FRL training before DP Link trainingAnkit Nautiyal
2020-12-07drm/i915/dp: No need to poll FEC Enable Live bitManasi Navare
2020-12-03drm/i915/ddi: Track power reference taken for encoder main lane AUX useImre Deak
2020-12-03drm/i915/ddi: Track power reference taken for encoder DDI IO useImre Deak
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-07-18 07:37:15 +0000