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path: root/drivers/gpu/drm/i915/display/intel_dsb.c
AgeCommit message (Expand)Author
2024-08-29drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is doneVille Syrjälä
2024-08-29drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANKVille Syrjälä
2024-08-29drm/i915/dsb: Introduce intel_dsb_chain()Ville Syrjälä
2024-08-29drm/i915/dsb: Introduce intel_dsb_wait_scanline_{in,out}()Ville Syrjälä
2024-08-29drm/i915/dsb: Precompute DSB_CHICKENVille Syrjälä
2024-08-29drm/i915/dsb: Account for VRR properly in DSB scanline stuffVille Syrjälä
2024-08-29drm/i915/dsb: Fix dewake scanlineVille Syrjälä
2024-08-29drm/i915/dsb: Shuffle code aroundVille Syrjälä
2024-08-29drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlierVille Syrjälä
2024-08-29drm/i915/dsb: Hook up DSB error interruptsVille Syrjälä
2024-06-20drm/i915/dsb: Add i915.enable_dsb module parameterVille Syrjälä
2024-06-20drm/i915/dsb: Convert the DSB code to use intel_display rather than i915Ville Syrjälä
2024-06-20drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare()Ville Syrjälä
2024-06-05drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()Ville Syrjälä
2024-06-05drm/i915/dsb: Move DSB ID definition to the headerVille Syrjälä
2024-06-05drm/i915/dsb: Polish the DSB ID enumVille Syrjälä
2024-05-31drm/i915: drop unnecessary i915_reg.h includesJani Nikula
2024-05-31drm/i915: Reuse intel_mode_vblank_start()Ville Syrjälä
2024-03-07drm/i915/dsb: Always set DSB_SKIP_WAITS_ENVille Syrjälä
2024-03-07drm/i915/dsb: Fix DSB vblank waits when using VRRVille Syrjälä
2024-02-23drm/i915/lnl: Program PKGC_LATENCY registerSuraj Kandpal
2024-01-05drm/i915: Disable DSB in Xe KMDJosé Roberto de Souza
2023-11-29drm/i915: correct the input parameter on _intel_dsb_commit()heminhong
2023-11-16drm/i915/dsb: DSB code refactoringAnimesh Manna
2023-10-13drm/i915/dsb: Correct DSB command buffer cache coherency settingsVille Syrjälä
2023-10-13drm/i915/dsb: Allocate command buffer from local memoryVille Syrjälä
2023-09-27drm/i915/dsb: Use DEwake to combat PkgC latencyVille Syrjälä
2023-09-27drm/i915/dsb: Add support for non-posted DSB registers writesVille Syrjälä
2023-09-27drm/i915/dsb: Introduce intel_dsb_reg_write_masked()Ville Syrjälä
2023-09-27drm/i915/dsb: Introduce intel_dsb_noop()Ville Syrjälä
2023-09-27drm/i915/dsb: Define the contents of some intstructions bit betterVille Syrjälä
2023-09-27drm/i915/dsb: Use non-locked register accessVille Syrjälä
2023-09-07drm/i915/dsb: Don't use indexed writes when byte enables are not all setVille Syrjälä
2023-09-07drm/i915/dsb: Avoid corrupting the first register writeVille Syrjälä
2023-09-07drm/i915/dsb: Dump the DSB command buffer when DSB failsVille Syrjälä
2023-03-30drm/i915/dsb: split out DSB regs to a separate fileJani Nikula
2023-02-20drm/i915/dsb: Nuke the DSB debugVille Syrjälä
2023-02-20drm/i915/dsb: Allow vblank synchronized DSB executionVille Syrjälä
2023-02-03drm/i915/dsb: Introduce intel_dsb_finish()Ville Syrjälä
2023-02-03drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()Ville Syrjälä
2023-02-03drm/i915/dsb: Pimp debug/error printsVille Syrjälä
2023-01-13drm/i915/dsb: Add mode DSB opcodesVille Syrjälä
2023-01-13drm/i915/dsb: Allow the caller to pass in the DSB buffer sizeVille Syrjälä
2023-01-13drm/i915/dsb: Introduce intel_dsb_align_tail()Ville Syrjälä
2023-01-13drm/i915/dsb: Handle the indexed vs. not inside the DSB codeVille Syrjälä
2023-01-13drm/i915/dsb: Improve the indexed reg write checksVille Syrjälä
2023-01-13drm/i915/dsb: Extract intel_dsb_emit()Ville Syrjälä
2023-01-13drm/i915/dsb: Extract assert_dsb_has_room()Ville Syrjälä
2023-01-13drm/i915/dsb: Fix DSB command buffer size checksVille Syrjälä
2023-01-13drm/i915/dsb: Align DSB register writes to 8 bytesVille Syrjälä
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