| Age | Commit message (Expand) | Author |
|---|
| 2024-04-17 | drm/i915: Suck snps/cx0 PLL states into dpll_hw_state | Ville Syrjälä |
| 2024-03-21 | drm/i915/display: use intel_encoder_is/to_* functions | Jani Nikula |
| 2024-03-21 | drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state() | Jani Nikula |
| 2023-12-04 | drm/i915/display: Don't use "proxy" headers | Andy Shevchenko |
| 2023-10-16 | drm/i915/display: Clean up zero initializers | Ville Syrjälä |
| 2023-10-07 | drm/i915: Simplify snps/c10x DPLL state checker calling convetion | Ville Syrjälä |
| 2023-10-07 | drm/i915: Constify the snps/c10x PLL state checkers | Ville Syrjälä |
| 2023-05-15 | drm/i915/display: add i915 parameter to I915_STATE_WARN() | Jani Nikula |
| 2023-04-15 | drm/i915: Make intel_{mpllb,c10pll}_state_verify() safer | Ville Syrjälä |
| 2023-02-24 | drm/i915/dg2: Add HDMI pixel clock frequencies 267.30 and 319.89 MHz | Ankit Nautiyal |
| 2023-01-18 | drm/i915: move snps_phy_failed_calibration to display sub-struct under snps | Jani Nikula |
| 2022-12-08 | drm/i915/snps: switch to intel_de_* register accessors in display code | Jani Nikula |
| 2022-11-11 | drm/i915: stop including i915_irq.h from i915_trace.h | Jani Nikula |
| 2022-08-24 | drm/i915/dg2: Add additional HDMI pixel clock frequencies | Taylor, Clinton A |
| 2022-06-17 | drm/i915/mpllb: move mpllb state check to intel_snps_phy.c | Jani Nikula |
| 2022-05-31 | drm/i915: Require an exact DP link freq match for the DG2 PLL | Ville Syrjälä |
| 2022-05-25 | drm/i915/dg2: Support 4k@30 on HDMI | Vandita Kulkarni |
| 2022-02-24 | drm/i915/dg2: Skip output init on PHY calibration failure | Matt Roper |
| 2022-02-18 | drm/i915/dg2: Drop 38.4 MHz MPLLB tables | Matt Roper |
| 2022-02-18 | drm/i915: Fix for PHY_MISC_TC1 offset | Jouni Högander |
| 2022-02-17 | drm/i915/dg2: Print PHY name properly on calibration error | Matt Roper |
| 2022-01-24 | drm/i915/snps: convert to drm device based logging | Jani Nikula |
| 2022-01-11 | drm/i915: Move SNPS PHY registers to their own header | Matt Roper |
| 2021-12-07 | drm/i915/snps: use div32 version of MPLLB word clock for UHBR | Jani Nikula |
| 2021-11-03 | drm/i915: Query the vswing levels per-lane for snps phy | Ville Syrjälä |
| 2021-10-14 | drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs | Ville Syrjälä |
| 2021-10-04 | drm/i915: Pass the lane to intel_ddi_level() | Ville Syrjälä |
| 2021-10-04 | drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() | Ville Syrjälä |
| 2021-10-04 | drm/i915: Nuke useless .set_signal_levels() wrappers | Ville Syrjälä |
| 2021-09-30 | drm/i915: s/ddi_translations/trans/ | Ville Syrjälä |
| 2021-08-30 | drm/i915/dg2: UHBR tables added for pll programming | Animesh Manna |
| 2021-08-26 | drm/i915/snps: constify struct intel_mpllb_state arrays harder | Jani Nikula |
| 2021-08-13 | drm/i915/dg2: use existing mechanisms for SNPS PHY translations | Jani Nikula |
| 2021-07-29 | drm/i915/dg2: Update lane disable power state during PSR | Gwan-gyeong Mun |
| 2021-07-29 | drm/i915/dg2: Wait for SNPS PHY calibration during display init | Matt Roper |
| 2021-07-29 | drm/i915/dg2: Add vswing programming for SNPS phys | Matt Roper |
| 2021-07-29 | drm/i915/dg2: Add MPLLB programming for HDMI | Matt Roper |
| 2021-07-29 | drm/i915/dg2: Add MPLLB programming for SNPS PHY | Matt Roper |
