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path: root/drivers/gpu/drm/i915/display/skl_universal_plane.c
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2024-11-06Merge tag 'drm-intel-next-2024-11-04' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next drm/i915 feature pull #2 for v6.13: Features and functionality: - Pantherlake (PTL) Xe3 LPD display enabling for xe driver (Clint, Suraj, Dnyaneshwar, Matt, Gustavo, Radhakrishna, Chaitanya, Haridhar, Juha-Pekka, Ravi) - Enable dbuf overlap detection on Lunarlake and later (Stanislav, Vinod) - Allow fastset for HDR infoframe changes (Chaitanya) - Write DP source OUI also for non-eDP sinks (Imre) Refactoring and cleanups: - Independent platform identification for display (Jani) - Display tracepoint fixes and cleanups (Gustavo) - Share PCI ID headers between i915 and xe drivers (Jani) - Use x100 version for full version and release checks (Jani) - Conversions to struct intel_display (Jani, Ville) - Reuse DP DPCD and AUX macros in gvt instead of duplication (Jani) - Use string choice helpers (R Sundar, Sai Teja) - Remove unused underrun detection irq code (Sai Teja) - Color management debug improvements and other cleanups (Ville) - Refactor panel fitter code to a separate file (Ville) - Use try_cmpxchg() instead of open-coding (Uros Bizjak) Fixes: - PSR and Panel Replay fixes and workarounds (Jouni) - Fix panel power during connector detection (Imre) - Fix connector detection and modeset races (Imre) - Fix C20 PHY TX MISC configuration (Gustavo) - Improve panel fitter validity checks (Ville) - Fix eDP short HPD interrupt handling while runtime suspended (Imre) - Propagate DP MST DSC BW overhead/slice calculation errors (Imre) - Stop hotplug polling for eDP connectors (Imre) - Workaround panels reporting bad link status after PSR enable (Jouni) - Panel Replay VRR VSC SDP related workaround and refactor (Animesh, Mitul) - Fix memory leak on eDP init error path (Shuicheng) - Fix GVT KVMGT Kconfig dependencies (Arnd Bergmann) - Fix irq function documentation build warning (Rodrigo) - Add platform check to power management fuse bit read (Clint) - Revert kstrdup_const() and kfree_const() usage for clarity (Christophe JAILLET) - Workaround horizontal odd panning issues in display versions 20 and 30 (Nemesa) - Fix xe drive HDCP GSC firmware check (Suraj) Merges: - Backmerge drm-next to get some KVM changes (Rodrigo) - Fix a build failure originating from previous backmerge (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> # Conflicts: # drivers/gpu/drm/i915/display/intel_dp_mst.c From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87h68ni0wd.fsf@intel.com
2024-10-29drm/i915/xe3lpd: Move async flip bit to PLANE_SURF registerDnyaneshwar Bhadane
The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD. Bspec: 69853,69878 Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com> Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241028193015.3241858-7-clinton.a.taylor@intel.com
2024-10-29drm/i915/xe3lpd: Increase resolution for plane to support 6kSuraj Kandpal
DISPLAY_VER >= 30 onwards CRTC can now support 6k resolution. Increase pipe and plane max width and height to reflect this increase in resolution. --v2 -Take care of the subsampling scenario sooner rather than later [Matt] --v3 -Take care of the joined pipe limits too [Ankit/Matt] --v4 -Leave the joiner limits check here as is and handle them later [Ville] Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241028074333.182041-2-suraj.kandpal@intel.com
2024-10-18Merge tag 'drm-xe-next-2024-10-17' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next UAPI Changes: - (Implicit) Fix the exec unnecessary implicit fencing (Matt Brost) Driver Changes: - Fix an inverted if statement (Colin) - Fixes around display d3cold vs non-d3cold runtime pm (Imre) - A couple of scheduling fixes (Matt Brost) - Increase a query timestamp witdh (Lucas) - Move a timestamp read (Lucas) - Tidy some code using multiple put_user() (Lucas) - Fix an ufence signaling error (Nirmoy) - Initialize the ufence.signalled field (Matt Auld) - Display fb alignement work (Juha-Pekka) - Disallow horisontal flip with tile4 + display20 (Juha-Pekka) - Extend a workaround (Shekhar) - Enlarge the global invalidation timeout (Shuicheng) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Hellstrom <thomas.hellstrom@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZxDZaRRQAzrG1uir@fedora
2024-10-15drm/i915/display: Don't allow tile4 framebuffer to do hflip on display20 or ↵Juha-Pekka Heikkila
greater On display ver 20 onwards tile4 is not supported with horizontal flip Bspec: 69853 Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241007182841.2104740-1-juhapekka.heikkila@gmail.com
2024-10-09drm/i915: s/gen12/tgl/ in the universal plane codeVille Syrjälä
Using "gen12" in display code is not desirable. Replace it with "tgl" to match how we talk about other platforms in the same code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240918144445.5716-8-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2024-10-09drm/i915: Drop GEN12_MC_CCS check from skl_plane_max_width()Ville Syrjälä
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS is tgl+ only, so checking for it in skl_plane_max_width() (which only applies to pre-glk hardware) is pointless. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240918144445.5716-7-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2024-10-09drm/i915: Enable fp16 + CCS on TGL+Ville Syrjälä
TGL+ support compressed fp16 scanout. Enable it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240918144445.5716-6-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2024-10-09drm/i915: Enable 10bpc + CCS on ICLVille Syrjälä
ICL also supports compressed 10bpc scanout. Enable it. v2: Set .depth=30 for all variants to match drm_fourcc.c Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240918144445.5716-5-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2024-10-09drm/i915: Enable 10bpc + CCS on TGL+Ville Syrjälä
TGL+ support 10bpc compressed scanout. Enable it. v2: Set .depth=30 for all variants to match drm_fourcc.c Set clear color block size to 0x0 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240918144445.5716-4-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2024-10-04drm/i915: Plumb 'dsb' all way to the plane hooksVille Syrjälä
We need to be able to do both MMIO and DSB based pipe/plane programming. To that end plumb the 'dsb' all way from the top into the plane commit hooks. The compiler appears smart enough to combine the branches from all the back-to-back register writes into a single branch. So the generated asm ends up looking more or less like this: plane_hook() { if (dsb) { intel_dsb_reg_write(); intel_dsb_reg_write(); ... } else { intel_de_write_fw(); intel_de_write_fw(); ... } } which seems like a reasonably efficient way to do this. An alternative I was also considering is some kind of closure (register write function + display vs. dsb pointer passed to it). That does result is smaller code as there are no branches anymore, but having each register access go via function pointer sounds less efficient. Not that I actually measured the overhead of either approach yet. Also the reg_rw tracepoint seems to be making a huge mess of the generated code for the mmio path. And additionally there's some kind of IS_GSI_REG() hack in __raw_uncore_read() which ends up generating a pointless branch for every mmio register access. So looks like there might be quite a bit of room for improvement in the mmio path still. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240930170415.23841-12-ville.syrjala@linux.intel.com
2024-09-19drm/i915/display: convert skl_universal_plane.c to struct drm_gem_objectJani Nikula
Prefer the driver agnostic struct drm_gem_object over i915 specific struct drm_i915_gem_object. Add new intel_bo_* functions as needed. Convert intel_pxp_key_check() to struct drm_gem_object. Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0a6d2bec50764efaae4322c9cfa33eefbfe1c054.1726589119.git.jani.nikula@intel.com
2024-09-11drm/i915/display: Fix BMG CCS modifiersJuha-Pekka Heikkila
Let I915_FORMAT_MOD_4_TILED_BMG_CCS show up as supported modifier Fixes: 97c6efb36497 ("drm/i915/display: Plane capability for 64k phys alignment") Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240902074021.459480-1-juhapekka.heikkila@gmail.com Signed-off-by: Maarten Lankhorst,,, <maarten.lankhorst@linux.intel.com> (cherry picked from commit c4d37c54c3739530f8585ccf064fb712913f8375) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2024-09-04drm/i915/display: Fix BMG CCS modifiersJuha-Pekka Heikkila
Let I915_FORMAT_MOD_4_TILED_BMG_CCS show up as supported modifier Fixes: 97c6efb36497 ("drm/i915/display: Plane capability for 64k phys alignment") Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240902074021.459480-1-juhapekka.heikkila@gmail.com Signed-off-by: Maarten Lankhorst,,, <maarten.lankhorst@linux.intel.com>
2024-08-30Merge tag 'drm-intel-next-2024-08-29' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Cross-driver (xe-core) Changes: - Require BMG scanout buffers to be 64k physically aligned (Maarten) Core (drm) Changes: - Introducing Xe2 ccs modifiers for integrated and discrete graphics (Juha-Pekka) Driver Changes: - General cleanup and more work moving towards intel_display isolation (Jani) - New display workaround (Suraj) - Use correct cp_irq_count on HDCP (Suraj) - eDP PSR fix when CRC is enabled (Jouni) - Fix DP MST state after a sink reset (Imre) - Fix Arrow Lake GSC firmware version (John) - Use chained DSBs for LUT programming (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZtCC0lJ0Zf3MoSdW@intel.com
2024-08-22drm/{i915, xe}: Avoid direct inspection of dpt_vma from outside dptRodrigo Vivi
DPT code is so dependent on i915 vma implementation and it is not ported yet to Xe. This patch limits inspection to DPT's VMA struct to intel_dpt component only, so the Xe GGTT code can evolve. Cc: Matthew Brost <matthew.brost@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240821193842.352557-4-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-08-21drm/i915/display: allow creation of Xe2 ccs framebuffersJuha-Pekka Heikkila
Add I915_FORMAT_MOD_4_TILED_BMG_CCS and I915_FORMAT_MOD_4_TILED_LNL_CCS to possible created modifier for new framebuffer on Xe driver. Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240816115229.531671-4-juhapekka.heikkila@gmail.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-08-21drm/i915/display: Don't enable decompression on Xe2 with Tile4Juha-Pekka Heikkila
>From now on expect Tile4 not to be using compression Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240816115229.531671-2-juhapekka.heikkila@gmail.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-06-24drm/i915: Nuke the TGL+ chroma plane tile row alignment stuffVille Syrjälä
I don't think the display hardware really has such chroma plane tile row alignment requirements as outlined in commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") Bspec had the same exact thing to say about earlier hardware as well, but we never cared and things work just fine. The one thing mentioned in that commit that is definitely true however is the fence alignment issue. But we don't deal with that on earlier hardware either. We do have code to deal with that issue for the first color plane, but not the chroma planes. So I think if we did want to check this more extensively we should do it in the same places where we already check the first color plane (namely convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()). Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-10-ville.syrjala@linux.intel.com
2024-06-24drm/i915: Update plane alignment requirements for TGL+Ville Syrjälä
Currently we still use the SKL+ PLANE_SURF alignment even for TGL+ even though the hardware no longer needs it. Introduce a separate tgl_plane_min_alignment() and update it to more accurately reflect the hardware requirements. v2: Don't screw up DPT+semiplanar 2MiB alignment Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-9-ville.syrjala@linux.intel.com
2024-06-24drm/i915: Move intel_surf_alignment() into skl_univerals_plane.cVille Syrjälä
Now that all pre-skl platforms have their own .min_alignment() functions the remainder of intel_surf_alignment() can be hoisted into skl_univerals_plane.c (and renamed appropriately). Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-8-ville.syrjala@linux.intel.com
2024-06-24drm/i915: Introduce the plane->min_alignment() vfuncVille Syrjälä
Different hardware generations have different scanout alignment requirements. Introduce a new vfunc that will allow us to make that distinction without horrible if-ladders. For now we directly plug in the existing intel_surf_alignment() and intel_cursor_alignment() functions. For fbdev we (temporarily) introduce intel_fbdev_min_alignment() that simply queries the alignment from the primary plane of the first crtc. TODO: someone will need to fix xe's alignment handling Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-4-ville.syrjala@linux.intel.com Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-06-12drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy
Lets unify both bigjoiner and ultrajoiner under simple "joiner" name, because in future we might have multiple configurations, involving multiple bigjoiners, ultrajoiner, however it is possible to use same api for handling both. v2: - Renamed back some bigjoiner specific parts for now(Ville) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> [vsyrjala: Catch a few more cases] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607075457.15700-1-stanislav.lisovskiy@intel.com
2024-06-03drm/i915/display: Selective fetch Y position on Region Early TransportJouni Högander
Selective fetch Y position differs when Region Early Transport is used. Use formula from Bspec for this. Bspec: 68927 Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-5-jouni.hogander@intel.com
2024-05-22drm/i915: Add separate defines for cursor WM/DDB register bitsVille Syrjälä
Make a more thorough split between universal planes vs. cursors by defining the contents of the cursor WM/DDB registers separately. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-22drm/i915: Rename selective fetch plane registersVille Syrjälä
Rename the selective fetch plane registers to match the spec. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-22drm/i915: Add skl+ plane name aliases to enum plane_idVille Syrjälä
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch of unnecessary head scratching. Add aliases using the skl+ plane names. And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1 as we only ever have 0-2 sprites per pipe on those platforms. v2: Don't break icl_nv12_y_plane_mask() (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517171208.21313-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-15drm/i915: Handle SKL+ WM/DDB registers next to all other plane registersVille Syrjälä
Having the plane WM/DDB regitster write functions in skl_watermarks.c is rather annoying when trying to implement DSB based plane updates. Move them into the respective files that handle all other plane register writes. Less places where I need to worry about the DSB vs. MMIO decisions. The downside is that we spread the wm struct details a bit further afield. But if that becomes too annoying we can probably abstract things a bit more with a few extra functions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-17-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-15drm/i915: Extract skl_universal_plane_regs.hVille Syrjälä
Move most of the SKL+ universal plane register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-10drm/i915: Polish types in fb calculationsVille Syrjälä
Be a bit more consistent in our use of integer types in the fb related calculatiosn. u32 we generally only use for ggtt offsets and such, and everything else can be regular (unsigned) ints. There's also an overabundance of consts for local variables in skl_check_main_surface() which is not something we generally do. So get rid of those while at it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-10drm/i915: Clean up skl+ plane stride limitsVille Syrjälä
skl_plane_max_stride() is pretty messy. Streamline it and split it into clear skl+ vs. adl+ variants. TODO: Deal with icl and tgl strude limits properly Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-03drm/i915: s/need_async_flip_disable_wa/need_async_flip_toggle_wa/Ville Syrjälä
Rename need_async_flip_disable_wa to need_async_flip_toggle_wa to better reflect the fact that we need to deal with the bad PLANE_CTL_ASYNC_FLIP double buffering behaviour going both ways. Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430095639.26390-6-ville.syrjala@linux.intel.com
2024-05-03drm/i915: Eliminate extra frame from skl-glk sync->async flip changeVille Syrjälä
On bdw-glk the sync->async flip change takes an extra frame due to the double buffering behaviour of the async flip plane control bit. Since on skl+ we are now explicitly converting the first async flip to a sync flip (in order to allow changing the modifier and/or ddb/watermarks) we are now taking two extra frames until async flips are actually active. We can drop that back down to one frame by setting the async flip bit already during the sync flip. Note that on bdw we don't currently do the extra sync flip (see intel_plane_do_async_flip()) so technically we wouldn't have to deal with this in i9xx_plane_update_arm(). But I added the relevant snippet of code there as well, just in case we ever decide to go for the extra sync flip on pre-skl platforms as well (we might, for example, want to change the fb stride). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430095639.26390-5-ville.syrjala@linux.intel.com Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
2024-03-06drm/i915/display: Disable AuxCCS framebuffers if built for XeJuha-Pekka Heikkila
AuxCCS framebuffers don't work on Xe driver hence disable them from plane capabilities until they are fixed. FlatCCS framebuffers work and they are left enabled. CCS is left untouched for i915 driver. Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/933 Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Tested-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Fixes: 44e694958b95 ("drm/xe/display: Implement display support") Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240228140225.858145-1-juhapekka.heikkila@gmail.com
2024-02-08drm/i915/display: On Xe2 always enable decompression with tile4Juha-Pekka Heikkila
With Xe2 always treat tile4 as if it was using flat ccs. Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240202150602.430036-2-juhapekka.heikkila@gmail.com
2024-02-07drm/i915: Try to relocate the BIOS fb to the start of ggttVille Syrjälä
On MTL the GOP (for whatever reason) likes to bind its framebuffer high up in the ggtt address space. This can conflict with whatever ggtt_reserve_guc_top() is trying to do, and the result is that ggtt_reserve_guc_top() fails and then we proceed to explode when trying to tear down the driver. Thus far I haven't analyzed what causes the actual fireworks, but it's not super important as even if it didn't explode we'd still fail the driver load and the user would be left with an unusable GPU. To remedy this (without having to figure out exactly what ggtt_reserve_guc_top() is trying to achieve) we can attempt to relocate the BIOS framebuffer to a lower ggtt address. We can do this at this early point in driver init because nothing else is supposed to be clobbering the ggtt yet. So we simply change where in the ggtt we pin the vma, the original PTEs will be left as is, and the new PTEs will get written with the same dma addresses. The plane will keep on scanning out from the original PTEs until we are done with the whole process, and at that point we rewrite the plane's surface address register to point at the new ggtt address. Since we don't need a specific ggtt address for the plane (apart from needing it to land in the mappable region for normal stolen objects) we'll just try to pin it without a fixed offset first. It should end up at the lowest available address (which really should be 0 at this point in the driver init). If that fails we'll fall back to just pinning it exactly to the origianal address. To make sure we don't accidentlally pin it partially over the original ggtt range (as that would corrupt the original PTEs) we reserve the original range temporarily during this process. v2: Try to pin explicitly to ggtt offset 0 as otherwise DG2 puts it even higher (atm we have no PIN_LOW flag to force it low) v3: "fix" xe Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Tested-by: Paz Zcharya <pazz@chromium.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240202224340.30647-16-ville.syrjala@linux.intel.com Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
2023-11-27drm/i915/psr: Add proper handling for disabling sel fetch for planesJouni Högander
Currently we are enabling selective fetch for all planes that are visible. This is suboptimal as we might be fetching for memory for planes that are not part of selective update. Fix this by adding proper handling for disabling plane selective fetch: If plane previously part of selective update is now not part of update: Add it into updated planes and let the plane configuration to disable selective fetch for it. v3: Checkpatch warnings fixed v2: - Add setting sel_fetch_area->y1/y2 to -1 - Remove setting again local sel_fetch_area variable Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231120082606.3156488-3-jouni.hogander@intel.com
2023-11-27drm/i915/psr: Move plane sel fetch configuration into plane source filesJouni Högander
Currently selective fetch configuration for planes is implemented in psr code. More suitable place for this code is where everything else is configured for planes -> move it into skl_universal_plane.c and intel_cursor.c. This also allows us to drop hooks for cursor handling. v3: Checkpatch warnings fixed v2: Removed setting sel_fetch_area->y1/y2 as -1 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231120082606.3156488-2-jouni.hogander@intel.com
2023-11-23drm/i915/display: in skl_surf_address check for dpt-vmaJuha-Pekka Heikkila
touch dpt_vma->node only if dpt-vma is not NULL Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231116150225.204233-2-juhapekka.heikkila@gmail.com
2023-11-11drm/i915: remove excess functions from plane protection checkJani Nikula
Reduce the function calls by reusing ->decrypt. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231109160722.3372379-2-jani.nikula@intel.com
2023-11-11drm/i915: abstract plane protection checkJani Nikula
Centralize the conditions in a function. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231109160722.3372379-1-jani.nikula@intel.com
2023-10-26drm/i915/display: Move enable_dpt module parameter under displayJouni Högander
Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231024124109.384973-11-jouni.hogander@intel.com
2023-10-23drm/i915: drop gt/intel_gt.h include from skl_universal_plane.cJani Nikula
No longer needed after commit 94bcf876cb6a ("drm/i915/mtl: Drop Wa_14017240301"). Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231011142704.985867-1-jani.nikula@intel.com
2023-10-04Merge drm/drm-next into drm-intel-nextJani Nikula
Backmerge to sync up with drm-intel-gt-next and drm-misc-next. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2023-10-03drm/i915/lnl: possibility to enable FBC on first three planesVinod Govindapillai
In LNL onwards, FBC can be associated to the first three planes. FBC will be enabled on planes first come first served basis until the userspace can select one of these FBC capable planes explicitly. v2: - avoid fbc->state.plane check in intel_fbc_check_plane (Ville) - simplify plane binding register writes (Matt) - Update the subject to reflect that fbc can be enabled only in the first three planes (Matt) v3: - use icl_is_hdr_plane(), use wrapper macro for plane binding register access, comments update and patch split (Ville) v4: - update to the plane binding register access macro Bspec: 69560 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230922133003.150578-2-vinod.govindapillai@intel.com
2023-10-03Merge tag 'drm-intel-gt-next-2023-09-28' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next Driver Changes: Fixes/improvements/new stuff: - Fix TLB-Invalidation seqno store [mtl] (Alan Previn) - Force a reset on internal GuC error [guc] (John Harrison) - Define GSC fw [gsc] (Daniele Ceraolo Spurio) - Update workaround 14016712196 [dg2/mtl] (Tejas Upadhyay) - Mark requests for GuC virtual engines to avoid use-after-free (Andrzej Hajda) - Add Wa_14015150844 [dg2/mtl] (Shekhar Chauhan) - Prevent error pointer dereference (Dan Carpenter) - Add Wa_18022495364 [tgl,adl,rpl] (Dnyaneshwar Bhadane) - Fix GuC PMU by moving execlist stats initialization to execlist specific setup (Umesh Nerlige Ramappa) - Fix PXP firmware load [pxp/mtl] (Alan Previn) - Fix execution/context state of PXP contexts (Alan Previn) - Limit the length of an sg list to the requested length (Matthew Wilcox) - Fix reservation address in ggtt_reserve_guc_top [guc] (Javier Pello) - Add Wa_18028616096 [dg2] (Shekhar Chauhan) - Get runtime pm in busyness worker only if already active [guc/pmu] (Umesh Nerlige Ramappa) - Don't set PIPE_CONTROL_FLUSH_L3 for aux inval (Nirmoy Das) Future platform enablement: - Fix and consolidate some workaround checks, make others IP version based [mtl] (Matt Roper) - Replace Meteorlake subplatforms with IP version checks (Matt Roper) - Adding DeviceID for Arrowlake-S under MTL [mtl] (Nemesa Garg) - Run relevant bits of debugfs drop_caches per GT (Tvrtko Ursulin) Miscellaneous: - Remove Wa_15010599737 [dg2] (Shekhar Chauhan) - Align igt_spinner_create_request with hangcheck [selftests] (Jonathan Cavitt) - Remove pre-production workarounds [dg2] (Matt Roper) - Tidy some workaround definitions (Matt Roper) - Wait longer for tasks in migrate selftest [gt] (Jonathan Cavitt) - Skip WA verification for GEN7_MISCCPCTL on DG2 [gt] (Andrzej Hajda) - Silence injected failure in the load via GSC path [huc] (Daniele Ceraolo Spurio) - Refactor deprecated strncpy (Justin Stitt) - Update RC6 mask for mtl_drpc [debugfs/mtl] (Badal Nilawar) - Remove a static inline that requires including i915_drv.h [gt] (Jani Nikula) - Remove inlines from i915_gem_execbuffer.c [gem] (Jani Nikula) - Remove gtt_offset from stream->oa_buffer.head/.tail [perf] (Ashutosh Dixit) - Do not disable preemption for resets (Tvrtko Ursulin) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZRVzL02VFuwIkcGl@tursulin-desk
2023-09-21drm/i915/xe2lpd: Don't try to program PLANE_AUX_DISTMatt Roper
Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded to 0 since compression isn't ready; we need to make sure this doesn't cause the display code to go back to trying to write this register. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-8-lucas.demarchi@intel.com
2023-09-07drm/i915/mtl: Drop Wa_14017240301Matt Roper
Drop Wa_14017240301, which is only relevant to pre-production MTL hardware. Although we usually wait a little bit longer to start dropping pre-production workarounds for a platform, it was suggested to eliminate this one slightly earlier because it's a bit unusual/ugly: this workaround is a display-specific workaround that requires matching on the graphics/GT IP version instead of the display IP version. Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230907000354.3729827-2-matthew.d.roper@intel.com
2023-08-31drm/i915: add minimal i915_gem_object_frontbuffer.hJani Nikula
Split out frontbuffer related declarations and static inlines from gem/i915_gem_object.h into new gem/i915_gem_object_frontbuffer.h. The main goal is to reduce header interdependencies. With gem/i915_gem_object.h including display/intel_frontbuffer.h, modification of the latter causes a whopping 300+ objects to be rebuilt, while many of the source files actually needing it aren't explicitly including it at all. After the change, only 21 objects depend on display/intel_frontbuffer.h, directly or indirectly. Cc: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230830085127.2416842-1-jani.nikula@intel.com
2023-08-21drm/i915: Eliminate IS_MTL_GRAPHICS_STEPMatt Roper
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none of these workarounds are actually tied to MTL as a platform; they only relate to the Xe_LPG graphics IP, regardless of what platform it appears in. At the moment MTL is the only platform that uses Xe_LPG with IP versions 12.70 and 12.71, but we can't count on this being true in the future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead that is purely based on IP version. IS_GFX_GT_IP_STEP() is also GT-based rather than device-based, which will help prevent mistakes where we accidentally try to apply Xe_LPG graphics workarounds to the Xe_LPM+ media GT and vice-versa. v2: - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be used for both graphics and media IP (and any other kind of GTs that show up in the future). v3: - Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani) - Move macro to intel_gt.h. (Andi) v4: - Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and IS_GRAPHICS_STEP building blocks and name the parameters from/until rather than begin/fixed. (Jani) - Fix usage examples in comment. v5: - Tweak comment on macro. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-15-matthew.d.roper@intel.com
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