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Commit 723e8462a4fe ("pinctrl: qcom: spmi-gpio: Fix the GPIO strength
mapping") fixed a long-standing issue in the Qualcomm SPMI PMIC gpio
driver which had the 'low' and 'high' drive strength settings switched
but failed to update the debugfs interface which still gets this wrong.
Fix the debugfs code so that the exported values match the hardware
settings.
Note that this probably means that most devicetrees that try to describe
the firmware settings got this wrong if the settings were derived from
debugfs. Before the above mentioned commit the settings would have
actually matched the firmware settings even if they were described
incorrectly, but now they are inverted.
Fixes: 723e8462a4fe ("pinctrl: qcom: spmi-gpio: Fix the GPIO strength mapping")
Fixes: eadff3024472 ("pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver")
Cc: Anjelique Melendez <quic_amelende@quicinc.com>
Cc: stable@vger.kernel.org # 3.19
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/20241025121622.1496-1-johan+linaro@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add TLMM pinctrl driver to support pin configuration with pinctrl
framework for sm8750 SoC.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/20241112002843.2804490-3-quic_molvera@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The PM8937 provides 4 MPPs.
Add a compatible to support them.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/20241031-msm8917-v2-4-8a075faa89b1@mainlining.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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PM8937 has 8 GPIO-s with holes on GPIO3, GPIO4 and GPIO6.
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/20241031-msm8917-v2-2-8a075faa89b1@mainlining.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The use of of_property_read_bool() for non-boolean properties is
deprecated in favor of of_property_present() when testing for property
presence.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/20241104194437.327430-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add driver for the pincontrol device as present on the Qualcomm
SAR2130P platform. This is based on the msm-5.10 tree, tag
KERNEL.PLATFORM.1.0.r4-00400-NEO.0.
Co-developed-by: Mayank Grover <groverm@codeaurora.org>
Signed-off-by: Mayank Grover <groverm@codeaurora.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/20241018-sar2130p-tlmm-v2-2-11a1d09a6e5f@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for QCS8300 TLMM configuration and control via the
pinctrl framework.
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/20241018-qcs8300_tlmm-v3-2-8b8d3957cf1a@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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After commit 0edb555a65d1 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.
Convert all platform drivers below drivers/pinctrl to use .remove(),
with the eventual goal to drop struct platform_driver::remove_new(). As
.remove() and .remove_new() have the same prototypes, conversion is done
by just changing the structure member name in the driver initializer.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://lore.kernel.org/20241007205803.444994-8-u.kleine-koenig@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for QCS615 TLMM configuration and control via the
pinctrl framework.
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Link: https://lore.kernel.org/20240920-add_qcs615_pinctrl_driver-v2-2-e03c42a9d055@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The IPQ5424 SoC comes with a TLMM block, like all other Qualcomm
platforms, so add a driver for it.
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/20240927065244.3024604-6-quic_srichara@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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On X1E80100, GPIO interrupts for wakeup-capable pins have been broken since
the introduction of the pinctrl driver. This prevents keyboard and touchpad
from working on most of the X1E laptops. So far we have worked around this
by manually building a kernel with the "wakeup-parent" removed from the
pinctrl node in the device tree, but we cannot expect all users to do that.
Implement a similar workaround in the driver by clearing the wakeirq_map
for X1E80100. This avoids using the PDC wakeup parent for all GPIOs
and handles the interrupts directly in the pinctrl driver instead.
The PDC driver needs additional changes to support X1E80100 properly.
Adding a workaround separately first allows to land the necessary PDC
changes through the normal release cycle, while still solving the more
critical problem with keyboard and touchpad on the current stable kernel
versions. Bypassing the PDC is enough for now, because we have not yet
enabled the deep idle states where using the PDC becomes necessary.
Cc: stable@vger.kernel.org
Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver")
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/20240830-x1e80100-bypass-pdc-v1-1-d4c00be0c3e3@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Remove the erroneus 0x100000 offset to prevent the boards from crashing
on pin state setting, as well as for the intended state changes to take
effect.
Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver")
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/20240809-topic-h_sdc-v1-1-bb421532c531@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The current map seems to be out of sync (and includes a duplicate entry
for GPIO193..).
Replace it with the map present in shipping devices' ACPI tables.
This new one seems more complete, as it e.g. contains GPIO145 (PCIE6a
WAKE#)
Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Link: https://lore.kernel.org/20240711-topic-x1e_pdc_tlmm-v1-1-e278b249d793@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Some new drivers is the main part, the rest is cleanups and nonurgent
fixes.
Nothing much special about this, no core changes this time.
New drivers:
- Renesas RZ/V2H(P) SoC
- NXP Freescale i.MX91 SoC
- Nuvoton MA35D1 SoC
- Qualcomm PMC8380, SM4250, SM4250 LPI
Enhancements:
- A slew of scoped-based simplifications of of_node_put()"
* tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits)
pinctrl: renesas: rzg2l: Support output enable on RZ/G2L
pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions
pinctrl: renesas: rzg2l: Clarify OEN read/write support
dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description
dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function
dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties
pinctrl: freescale: Use scope based of_node_put() cleanups
pinctrl: equilibrium: Use scope based of_node_put() cleanups
pinctrl: ti: iodelay: Use scope based of_node_put() cleanups
pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32
pinctrl: cy8c95x0: Update cache modification
pinctrl: cy8c95x0: Use cleanup.h
pinctrl: renesas: r8a779h0: Remove unneeded separators
pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function
pinctrl: renesas: r8a779g0: Remove unneeded separators
pinctrl: renesas: r8a779h0: Add AVB MII pins and groups
pinctrl: renesas: r8a779g0: Fix TPU suffixes
pinctrl: renesas: r8a779g0: Fix TCLK suffixes
pinctrl: renesas: r8a779g0: FIX PWM suffixes
pinctrl: renesas: r8a779g0: Fix IRQ suffixes
...
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Account for more than only 23 GPIOs in LPASS Low Power Island pinctrl
generic driver. The previous value 23 was chosen to satisfy existing
SoC-specific drivers. However SM4250 LPI pinctrl uses more than 23 GPIOs
and its probe routine fails on:
if (WARN_ON(data->npins > MAX_NR_GPIO))
return -EINVAL;
with the following message:
[ 10.709014] ------------[ cut here ]------------
[ 10.719085] WARNING: CPU: 1 PID: 56 at
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:446
lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi]
[ 10.719108] Modules linked in: [...]
[ 10.719238] CPU: 1 PID: 56 Comm: kworker/u33:0 Not tainted
6.10.0-rc2-00012-ge45ddb1f8d34-dirty #7
[ 10.719245] Hardware name: Qualcomm Technologies, Inc. QRB4210 RB2 (DT)
[ 10.719250] Workqueue: events_unbound deferred_probe_work_func
[ 10.719265] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 10.719271] pc : lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi]
[ 10.719278] lr : lpi_pinctrl_probe+0x44/0x388 [pinctrl_lpass_lpi]
...
[ 10.719357] Call trace:
[ 10.719361] lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi]
[ 10.719369] platform_probe+0x68/0xc4
[ 10.719378] really_probe+0xbc/0x29c
[ 10.719384] __driver_probe_device+0x78/0x12c
[ 10.719390] driver_probe_device+0xd8/0x15c
[ 10.719395] __device_attach_driver+0xb8/0x134
[ 10.719401] bus_for_each_drv+0x88/0xe8
[ 10.719407] __device_attach+0xa0/0x190
[ 10.719412] device_initial_probe+0x14/0x20
[ 10.719418] bus_probe_device+0xac/0xb0
[ 10.719423] deferred_probe_work_func+0x88/0xc0
[ 10.719429] process_one_work+0x150/0x294
[ 10.719439] worker_thread+0x2f8/0x408
[ 10.719445] kthread+0x110/0x114
[ 10.719452] ret_from_fork+0x10/0x20
[ 10.719459] ---[ end trace 0000000000000000 ]---
[ 10.719589] qcom-sm4250-lpass-lpi-pinctrl a7c0000.pinctrl: probe
with driver qcom-sm4250-lpass-lpi-pinctrl failed with error -22
Fixes: c2e5a25e8d88 ("pinctrl: qcom: Introduce SM4250 LPI pinctrl driver")
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/20240627003654.242870-1-alexey.klimov@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for the pin controller block on SM4250 Low Power Island.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-2-a0342e47e21b@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The PDC was hooked up as a wakeup parent in the DTS in
commit 71f080633d1e ("arm64: dts: qcom: sdm670: Hook up PDC as
wakeup-parent of TLMM"), but the wakeirq mapping was not defined so it
had no effect. Add the mapping for wakeup interrupts on the PDC to their
corresponding pins.
Configuring a pin IRQ as dual-edge would break it unless the
wakeirq_dual_edge_errata flag is set.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20240523230619.256882-2-mailingradian@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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PMC8380 is a new chip, featuring 10 GPIOs. Describe it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-2-2de50cb28ac1@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The SPMI GPIO driver assumes that the parent device is an SPMI device
and accesses random data when backcasting the parent struct device
pointer for non-SPMI devices.
Fortunately this does not seem to cause any issues currently when the
parent device is an I2C client like the PM8008, but this could change if
the structures are reorganised (e.g. using structure randomisation).
Notably the interrupt implementation is also broken for non-SPMI devices.
Also note that the two GPIO pins on PM8008 are used for interrupts and
reset so their practical use should be limited.
Drop the broken GPIO support for PM8008 for now.
Fixes: ea119e5a482a ("pinctrl: qcom-pmic-gpio: Add support for pm8008")
Cc: stable@vger.kernel.org # 5.13
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240529162958.18081-9-johan+linaro@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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SDC1 and UFS_RESET special pins are located in the west memory bank.
SDC1 have address 0x359a000:
0x3500000 (TLMM BASE) + 0x0 (WEST) + 0x9a000 (SDC1_OFFSET) = 0x359a000
UFS_RESET have address 0x359f000:
0x3500000 (TLMM BASE) + 0x0 (WEST) + 0x9f000 (UFS_OFFSET) = 0x359a000
Fixes: b915395c9e04 ("pinctrl: qcom: Add SM7150 pinctrl driver")
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Message-ID: <20240423203245.188480-1-danila@jiaxyga.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add MODULE_DEVICE_TABLE(), so the module could be properly autoloaded
based on the alias from of_device_id table. Pin controllers are
considered core components, so usually they are built-in, however these
can be built and used as modules on some generic kernel.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Message-ID: <20240411064614.7409-4-krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for qcom,pmih0108-gpio and qcom,pmd8028-gpio.
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Message-ID: <20240326220628.2392802-5-quic_amelende@quicinc.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for qcom,pmxr2230-gpio and qcom,pm6450-gpio.
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Message-ID: <20240326220628.2392802-4-quic_amelende@quicinc.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Use proper model name in SM8650 LPASS pin controller Kconfig entry.
Cc: <stable@vger.kernel.org>
Fixes: c4e47673853f ("pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240216102435.89867-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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remove the second #include <linux/seq_file.h>
Signed-off-by: Wang Jinchao <wangjinchao@xfusion.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/202312151810+0800-wangjinchao@xfusion.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add pinctrl driver for TLMM block found in SM4450 SoC.
Can Guo helped out in reviewing the driver.
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20231212094900.12615-3-quic_tengfan@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The pinconf-groups debugfs file dumps each valid configuration item of
all pin groups. Some platforms and devices may have pin groups which
cannot be accessed, according to commit 691bf5d5a7bf ("pinctrl: qcom:
Don't allow protected pins to be requested"). Fail for each
configuration item of an invalid pin group by checking the GPIO chip's
valid mask.
The validity of the pin group cannot be checked in the generic pinconf
dump (function "pinconf_generic_dump_one"), as it does not directly
interact with the gpiochip or the pinmux callbacks (which would give it
access to the request callback). Instead, an entry contains the ID and
name of the pingroup with no properties when all items fail.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20231128020202.728156-3-mailingradian@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The group is not used anywhere, remove it. And if needed, it should be
struct pingroup anyway.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231129161459.1002323-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Replace kernel.h with what exactly is being used, i.e. array_size.h.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231129161459.1002323-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add initial pinctrl driver to support pin configuration with pinctrl
framework for X1E80100 SoC.
Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231117093921.31968-3-quic_sibis@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Existing Qualcomm SoCs have the LPASS pin controller slew rate control
in separate register, however this will change with upcoming Qualcomm
SoCs. The slew rate will be part of the main register for pin
configuration, thus second device IO address space is not needed.
Prepare for supporting new SoCs by adding flag customizing the driver
behavior for slew rate.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231013145935.220945-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Setting slew rate for each pin will grow with upcoming Qualcomm SoCs,
so split the code responsible for this into separate function for easier
readability and maintenance.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231013145935.220945-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add Top Level Mode Multiplexer (pinctrl) support for the SM8650 platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-tlmm-v3-3-0e179c368933@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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New platforms uses a new set of bits to control the wakeirq
delivery to the PDC block.
The intr_wakeup_present_bit indicates if the GPIO supports
wakeirq and intr_wakeup_enable_bit enables wakeirq delivery
to the PDC block.
While the name seems to imply this only enables wakeup events,
it is required to allow interrupts events to the PDC block.
Enable this bit in the irq resource request/free if:
- gpio is in wakeirq map
- has the intr_wakeup_present_bit
- the intr_wakeup_enable_bit is set
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-tlmm-v3-2-0e179c368933@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add driver for the pin controller in Low Power Audio SubSystem (LPASS)
of Qualcomm SM8650 SoC.
Notable differences against SM8550 LPASS pin controller:
1. Additional address space for slew rate thus driver uses
LPI_FLAG_SLEW_RATE_SAME_REG and sets slew rate via different
register.
2. Two new pin mux functions: qca_swr_clk and qca_swr_data
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231027093615.140656-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"No pin control core changes this time.
New drivers:
- Realtek RTD family pin control driver and RTD1619B, RTD1319D and
RTD1315E subdrivers
- Nuvoton NPCM8xx combined pin control and GPIO driver
- Amlogic T7 pin control driver
- Renesas RZ/G3S pin control driver
Improvements:
- A number of additional UART groups added to the Mediatek MT7981
driver
- MPM pin maps added for Qualcomm MSM8996, SM6115, SM6125 and SDM660
- Extra GPIO banks for the Sunxi H616
- MLSP I2C6 function support in Qualcomm MSM8226
- Some __counted_by() annotations for dynamic arrays
- Ongoing work to make remove() return void
- LSBC groups and functions in the Renesas R8A7778"
* tag 'pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits)
pinctrl: Use device_get_match_data()
dt-bindings: pinctrl: qcom,sa8775p-tlmm: add missing wakeup-parent
dt-bindings: pinctrl: nuvoton,npcm845: Add missing additionalProperties on gpio child nodes
dt-bindings: pinctrl: brcm: Ensure all child node properties are documented
pinctrl: renesas: rzn1: Convert to platform remove callback returning void
pinctrl: renesas: rzg2l: Add RZ/G3S support
dt-bindings: pinctrl: renesas: Document RZ/G3S SoC
pinctrl: renesas: rzg2l: Add support for different DS values on different groups
pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration
pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S
pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets
pinctrl: renesas: rzg2l: Index all registers based on port offset
pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request()
pinctrl: renesas: r8a7778: Add LBSC pins, groups, and functions
pinctrl: intel: fetch community only when we need it
pinctrl: cherryview: reduce scope of PIN_CONFIG_BIAS_HIGH_IMPEDANCE case
pinctrl: cherryview: Convert to platform remove callback returning void
pinctrl: sprd-sc9860: Convert to platform remove callback returning void
pinctrl: qcom/msm: Convert to platform remove callback returning void
pinctrl: qcom/lpi: Convert to platform remove callback returning void
...
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The Qualcomm LPASS LPI pin controller driver uses one lock for guarding
Read-Modify-Write code for slew rate registers. However the pin
configuration and muxing registers have exactly the same RMW code but
are not protected.
Pin controller framework does not provide locking here, thus it is
possible to trigger simultaneous change of pin configuration registers
resulting in non-atomic changes.
Protect from concurrent access by re-using the same lock used to cover
the slew rate register. Using the same lock instead of adding second
one will make more sense, once we add support for newer Qualcomm SoC,
where slew rate is configured in the same register as pin
configuration/muxing.
Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
Cc: stable@vger.kernel.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231013145705.219954-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
To convert all those qcom pinctrl drivers, make msm_pinctrl_remove()
return void (instead of zero) and use .remove_new in all drivers.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20231009162510.335208-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
To convert all those qcom pinctrl drivers, make msm_pinctrl_remove()
return void (instead of zero) and use .remove_new in all drivers.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20231009162510.335208-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20231009083856.222030-19-u.kleine-koenig@pengutronix.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20231009083856.222030-18-u.kleine-koenig@pengutronix.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20231009083856.222030-17-u.kleine-koenig@pengutronix.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20231009083856.222030-16-u.kleine-koenig@pengutronix.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add pin <-> wakeirq mappings to allow for waking up the AP from sleep
through MPM-connected pins.
Signed-off-by: Matti Lehtimäki <matti.lehtimaki@gmail.com>
Reviewed-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20230923131432.21721-3-matti.lehtimaki@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add pin <-> wakeirq mappings to allow for waking up the AP from sleep
through MPM-connected pins.
Signed-off-by: Matti Lehtimäki <matti.lehtimaki@gmail.com>
Reviewed-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20230923131432.21721-2-matti.lehtimaki@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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On GPIO22 and GPIO23 there is another I2C bus. Add the function for it.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230922-msm8226-i2c6-v2-2-3fb55c47a084@z3ntu.xyz
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add pin <-> wakeirq mappings to allow for waking up the AP from sleep
through MPM-connected pins.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230809-topic-mpm_mappings-v2-4-4c2b4495e654@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Add pin <-> wakeirq mappings to allow for waking up the AP from sleep
through MPM-connected pins.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230809-topic-mpm_mappings-v2-3-4c2b4495e654@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Add pin <-> wakeirq mappings to allow for waking up the AP from sleep
through MPM-connected pins.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230809-topic-mpm_mappings-v2-2-4c2b4495e654@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Add pin <-> wakeirq mappings to allow for waking up the AP from sleep
through MPM-connected pins.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230809-topic-mpm_mappings-v2-1-4c2b4495e654@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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