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Age	Commit message (Expand)	Author
2021-02-08	clk: xilinx: move xlnx_vcu clock driver from soc	Michael Tretter
2021-02-08	soc: xilinx: vcu: fix alignment to open parenthesis	Michael Tretter
2021-02-08	soc: xilinx: vcu: fix repeated word the in comment	Michael Tretter
2021-02-08	soc: xilinx: vcu: use bitfields for register definition	Michael Tretter
2021-02-08	soc: xilinx: vcu: remove calculation of PLL configuration	Michael Tretter
2021-02-08	soc: xilinx: vcu: make the PLL configurable	Michael Tretter
2021-02-08	soc: xilinx: vcu: make pll post divider explicit	Michael Tretter
2021-02-08	soc: xilinx: vcu: implement clock provider for output clocks	Michael Tretter
2021-02-08	soc: xilinx: vcu: register PLL as fixed rate clock	Michael Tretter
2021-02-08	soc: xilinx: vcu: implement PLL disable	Michael Tretter
2021-02-08	soc: xilinx: vcu: add helpers for configuring PLL	Michael Tretter
2021-02-08	soc: xilinx: vcu: add helper to wait for PLL locked	Michael Tretter
2021-02-08	soc: xilinx: vcu: drop coreclk from struct xlnx_vcu	Michael Tretter
2020-12-09	soc: xilinx: vcu: use vcu-settings syscon registers	Michael Tretter
2020-12-09	soc: xilinx: vcu: drop useless success message	Michael Tretter
2020-01-06	remove ioremap_nocache and devm_ioremap_nocache	Christoph Hellwig
2018-01-16	soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv	Gustavo A. R. Silva
2018-01-08	soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver	Dhaval Shah