| Age | Commit message (Collapse) | Author |
|---|
|
SPI index mode has hardware limitation of reading only 64 bytes per
transaction due to fixed number of FIFO registers. This constraint leads
to performance issues when reading data from NAND/NOR flash devices, as the
controller must issue multiple requests to read 64-byte chunks, even if the
slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI
controller supports DMA mode, which allows reading up to 4 KB of data in
single transaction. This patch introduces changes to implement HID2 DMA
read support for the HID2 SPI controller.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Add changes to set the controller address mode before initiating commands.
The AMD SPI0 controller(AMDI0062) supports both 24-bit and 32-bit address
modes, while the HID2 SPI controller(AMDI0063) supports only the 24-bit
address mode. So this change is applicable only for SPI0 controller.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-8-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
AMD SoC has HID2 SPI controller in addition to the existing SPI0
controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its
version ID to the list of supported devices. Use the version ID to
differentiate the register offsets.
And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB
of data to be read in single transaction. Update the SPI-MEM support
function to reflect this capability.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Read and write the maximum number of data bytes at once, rather than byte
by byte. This improves AMD SPI controller driver performance by reducing
the time required to access FIFO registers. For example, with the new
changes, 64 bytes of data from the FIFO queue can be read in 8 read calls
(8 bytes per call) instead of 64 read calls(1 byte per call).
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
AMD SPI TX and RX counter registers are 1-byte length registers. The
existing value will be overwritten during register write, so masking is not
required.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-5-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
All `ioread*` and `iowrite*` functions are better suited for architecture
independent code to ensure portability across different architectures.
Since AMD SoCs support only the x86 architecture, replacing all `ioread*`
and `iowrite*` calls with `read*` and `write*` calls can reduce the
overhead of ensuring portability and increase the speed of I/O operations.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-4-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
The current spi_amd driver only supports single I/O mode, despite the AMD
SPI controller's capability for dual and quad I/O modes for read
operations. And AMD SPI0 controller has limited support for quad mode
write operations. Update the SPI-MEM support function to reflect these
hardware capabilities.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Sorting headers alphabetically helps locating duplicates, and makes it
easier to figure out where to insert new headers.
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-2-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Add support to the SPI controller driver to use SPI MEM framework.
SPI subsystem utilizing the SPI memory operations allows to re-use
SPI controller drivers for both SPI NOR devices, regular SPI devices
as well as SPI NAND devices.
Add below functions of spi_mem_ops to support SPI MEM framework
- exec-op(): to execute the memory operations.
- supports_op(): to check if the memory operation is supported.
- adjust_op_size(): to split data transfers so that they don’t exceed the
max transfer size supported by the controller.
Suggested-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1
causes:
spi-amd.c:401:21: error: cast to smaller integer type 'enum amd_spi_versions' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230810091247.70149-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Change legacy name master to modern name host or controller.
No functional changed.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20230728093221.3312026-2-yangyingliang@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Convert the users under SPI subsystem to SPI_CONTROLLER_HALF_DUPLEX.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20230710154932.68377-15-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
call
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother introduced four new APIs to get/set the
spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and
spi->cs_gpiod references with get or set API calls.
While adding multi-cs support in further patches the chip_select & cs_gpiod
members of the spi_device structure would be converted to arrays & the
"idx" parameter of the APIs would be used as array index i.e.,
spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver
Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi
Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver
Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part
Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
According to data sheet SPI_SPD7 should be set to 7.
Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20221104100637.13376-1-vitalyr@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
If the current speed is equal to the requested speed by the device
then return success.
This patch fixes a bug introduced by the commit 3fe26121dc3a
("spi: amd: Configure device speed") which checks speed_hz instead
of amd_spi->speed_hz.
Fixes: 3fe26121dc3a ("spi: amd: Configure device speed")
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Link: https://lore.kernel.org/r/20220830093607.45484-1-shreeya.patel@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Number of clock frequencies are supported by AMD controller
which are mentioned in the amd_spi_freq structure table.
Create mechanism to configure device clock frequency such
that it is strictly less than the requested frequency.
Give priority to the device transfer speed and in case
it is not set then use the max clock speed supported
by the device.
Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
The AMD SPI controller hardware seems to expect the FIFO buffer to be
fully setup with the details of all transfers in the SPI message before
it is able to start processing the data in a reliable way.
Furthermore, it imposes a strict ordering restriction, in the sense that
all TX transfers must be handled prior any RX transfer.
Hence, let's ensure amd_spi_execute_opcode() is called only once, after
all TX transfers have been setup, and process any remaining RX transfers
afterwards, in a second iteration.
Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and
improve error handling.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Provide documentation comments in the kernel-doc format
for enum amd_spi_versions and struct amd_spi.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20220706100626.1234731-6-cristian.ciocaltea@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
The io_base_addr member of struct amd_spi is not referenced anywhere
in the driver implementation and there is no indication that it could
be used in the future, hence drop it.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20220706100626.1234731-5-cristian.ciocaltea@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Simplify the error handling in probe function by switching from
dev_err() to dev_err_probe().
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20220706100626.1234731-4-cristian.ciocaltea@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Make use of the devm variant of spi_alloc_master() in order to cleanup
and simplify the error handling in the probe function by getting rid
of the goto statements.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20220706100626.1234731-3-cristian.ciocaltea@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Enabling the SPI CS35L41 audio codec driver for Steam Deck [1]
revealed a problem with the current AMD SPI controller driver
implementation, consisting of an unrecoverable system hang.
The issue can be prevented if we ensure the max transfer size
and the max message size do not exceed the FIFO buffer size.
According to the implementation of the downstream driver, the
AMD SPI controller is not able to handle more than 70 bytes per
transfer, which corresponds to the size of the FIFO buffer.
Hence, let's fix this by setting the SPI limits mentioned above.
[1] https://lore.kernel.org/r/20220621213819.262537-1-cristian.ciocaltea@collabora.com
Reported-by: Anastasios Vacharakis <vacharakis@o2mail.de>
Fixes: bbb336f39efc ("spi: spi-amd: Add AMD SPI controller driver support")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20220706100626.1234731-2-cristian.ciocaltea@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Commit 209043554915 ("spi: amd: Add support for version AMDI0062")
removed the cast ACPI_PTR() for no good reason. This wrapper is
important to make sure that the driver can be compiled with or without
CONFIG_ACPI enabled, useful for compiling test. Give back the cast so
compilation works again.
Fixes: 209043554915 ("spi: amd: Add support for version AMDI0062")
Signed-off-by: André Almeida <andrealmeid@collabora.com>
Link: https://lore.kernel.org/r/20220216162719.116062-1-andrealmeid@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Add support for the AMD SPI controller version AMDI0062. Do this in a
modular way where's easy to add new versions.
Signed-off-by: André Almeida <andrealmeid@collabora.com>
Link: https://lore.kernel.org/r/20220211143155.75513-4-andrealmeid@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
rom_addr is not used in the code, so we can just drop it from struct
amd_spi.
Signed-off-by: André Almeida <andrealmeid@collabora.com>
Link: https://lore.kernel.org/r/20220211143155.75513-3-andrealmeid@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Instead of implementing a custom IO busy wait function, just use
readl_poll_timeout().
Signed-off-by: André Almeida <andrealmeid@collabora.com>
Link: https://lore.kernel.org/r/20220211143155.75513-2-andrealmeid@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Return from a write-only transfer without waiting for
it to finish
But wait before a new transfer as the previous may
still happening and also wait before reading the data
from the FIFO
Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210910111529.12539-4-tanureal@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Remove internal cs from amd_spi
Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210910111529.12539-3-tanureal@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Use amd_spi_readreg32 to read 32 bits registers
Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210910111529.12539-2-tanureal@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Get master data in the start and then just use struct amd_spi
as it has the needed variable
Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Simplify this function implementation by using a known wrapper function.
Signed-off-by: Qing Zhang <zhangqing@loongson.cn>
Link: https://lore.kernel.org/r/1605930231-19448-1-git-send-email-zhangqing@loongson.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
Since ACPI_PTR() is used to NULLify the value when !CONFIG_ACPI,
struct 'spi_acpi_match' becomes defined but unused.
Fixes the following W=1 kernel build warning(s):
drivers/spi/spi-amd.c:297:36: warning: ‘spi_acpi_match’ defined but not used [-Wunused-const-variable=]
297 | static const struct acpi_device_id spi_acpi_match[] = {
| ^~~~~~~~~~~~~~
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Sanjay R Mehta <sanju.mehta@amd.com>
Link: https://lore.kernel.org/r/20200717135424.2442271-15-lee.jones@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
The AMD SPI driver stores a pointer to the spi_master in struct amd_spi
so that it can get from the latter to the former in amd_spi_fifo_xfer().
It's simpler to just pass the pointer from the sole caller
amd_spi_master_transfer() and drop the pointer from struct amd_spi.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: https://lore.kernel.org/r/a088b684ad292faf3bd036e51529e608e5c94638.1588590210.git.lukas@wunner.de
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
The AMD SPI driver calls spi_master_put() in its ->remove() hook even
though the preceding call to spi_unregister_master() already drops a
ref, thus leading to a refcount underflow. Drop the superfluous call
to spi_master_put().
This only leaves the call to spi_unregister_master() in the ->remove()
hook, so it's safe to change the ->probe() hook to use the devm version
of spi_register_master() and drop the ->remove() hook altogether.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: https://lore.kernel.org/r/5e53ccdf1eecd4e015dba99d0d77389107f8a2e3.1588590210.git.lukas@wunner.de
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
The AMD SPI driver calls platform_set_drvdata() on probe even though
it's already been set by __spi_alloc_controller(). Likewise, it calls
platform_set_drvdata() on remove even though it's going to be set by
__device_release_driver(). Drop the duplicate assignments.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: https://lore.kernel.org/r/499f8ad4759c2ff0f586e0459fb9a293faecff6d.1588590210.git.lukas@wunner.de
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
If probing fails, the AMD SPI driver pretends success to the driver core
by returning 0. Return the errno instead.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: https://lore.kernel.org/r/689f29a359718dab4f5de9ee66c02ea97b3bd9e8.1588590210.git.lukas@wunner.de
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
The AMD SPI driver uses devm_ioremap_resource() to map its registers, so
they're automatically unmapped via device_release() when the last ref on
the SPI controller is dropped. The additional iounmap() in the ->probe()
error path is thus unnecessary.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: https://lore.kernel.org/r/497cc38ae2beb7900ae05a1463eb83ff96e2770e.1588590210.git.lukas@wunner.de
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
In case of error, the function devm_ioremap_resource() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().
Fixes: bbb336f39efc ("spi: spi-amd: Add AMD SPI controller driver support")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20200429025426.167664-1-weiyongjun1@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
remove unused variable "opcode"
Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/1588049801-37995-1-git-send-email-sanju.mehta@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
This driver supports SPI Controller for AMD SOCs.This driver
supports SPI operations using FIFO mode of transfer.
Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
