blob: ca7ab6cf6fa53a7d09c3e1671ea868d2bfea2e0f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Intel Tangier GPIO functions
*
* Copyright (c) 2016, 2021, 2023 Intel Corporation.
*
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* Pandith N <pandith.n@intel.com>
* Raag Jadav <raag.jadav@intel.com>
*/
#ifndef _GPIO_TANGIER_H_
#define _GPIO_TANGIER_H_
#include <linux/gpio/driver.h>
#include <linux/pm.h>
#include <linux/spinlock_types.h>
#include <linux/types.h>
struct device;
struct tng_gpio_context;
/* Elkhart Lake specific wake registers */
#define GWMR_EHL 0x100 /* Wake mask */
#define GWSR_EHL 0x118 /* Wake source */
#define GSIR_EHL 0x130 /* Secure input */
/* Merrifield specific wake registers */
#define GWMR_MRFLD 0x400 /* Wake mask */
#define GWSR_MRFLD 0x418 /* Wake source */
#define GSIR_MRFLD 0xc00 /* Secure input */
/**
* struct tng_wake_regs - Platform specific wake registers
* @gwmr: Wake mask
* @gwsr: Wake source
* @gsir: Secure input
*/
struct tng_wake_regs {
u32 gwmr;
u32 gwsr;
u32 gsir;
};
/**
* struct tng_gpio_pinrange - Map pin numbers to gpio numbers
* @gpio_base: Starting GPIO number of this range
* @pin_base: Starting pin number of this range
* @npins: Number of pins in this range
*/
struct tng_gpio_pinrange {
unsigned int gpio_base;
unsigned int pin_base;
unsigned int npins;
};
#define GPIO_PINRANGE(gstart, gend, pstart) \
(struct tng_gpio_pinrange) { \
.gpio_base = (gstart), \
.pin_base = (pstart), \
.npins = (gend) - (gstart) + 1, \
}
/**
* struct tng_gpio_pin_info - Platform specific pinout information
* @pin_ranges: Pin to GPIO mapping
* @nranges: Number of pin ranges
* @name: Respective pinctrl device name
*/
struct tng_gpio_pin_info {
const struct tng_gpio_pinrange *pin_ranges;
unsigned int nranges;
const char *name;
};
/**
* struct tng_gpio_info - Platform specific GPIO and IRQ information
* @base: GPIO base to start numbering with
* @ngpio: Amount of GPIOs supported by the controller
* @first: First IRQ to start numbering with
*/
struct tng_gpio_info {
int base;
u16 ngpio;
unsigned int first;
};
/**
* struct tng_gpio - Platform specific private data
* @chip: Instance of the struct gpio_chip
* @reg_base: Base address of MMIO registers
* @irq: Interrupt for the GPIO device
* @lock: Synchronization lock to prevent I/O race conditions
* @dev: The GPIO device
* @ctx: Context to be saved during suspend-resume
* @wake_regs: Platform specific wake registers
* @pin_info: Platform specific pinout information
* @info: Platform specific GPIO and IRQ information
*/
struct tng_gpio {
struct gpio_chip chip;
void __iomem *reg_base;
int irq;
raw_spinlock_t lock;
struct device *dev;
struct tng_gpio_context *ctx;
struct tng_wake_regs wake_regs;
struct tng_gpio_pin_info pin_info;
struct tng_gpio_info info;
};
int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio);
extern const struct dev_pm_ops tng_gpio_pm_ops;
#endif /* _GPIO_TANGIER_H_ */
|
