1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
|
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "amdgpu_reset.h"
#include "aldebaran.h"
int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
struct amdgpu_reset_handler *handler)
{
/* TODO: Check if handler exists? */
list_add_tail(&handler->handler_list, &reset_ctl->reset_handlers);
return 0;
}
int amdgpu_reset_init(struct amdgpu_device *adev)
{
int ret = 0;
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_init(adev);
break;
default:
break;
}
return ret;
}
int amdgpu_reset_fini(struct amdgpu_device *adev)
{
int ret = 0;
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_fini(adev);
break;
default:
break;
}
return ret;
}
int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
struct amdgpu_reset_context *reset_context)
{
struct amdgpu_reset_handler *reset_handler = NULL;
if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
reset_handler = adev->reset_cntl->get_reset_handler(
adev->reset_cntl, reset_context);
if (!reset_handler)
return -ENOSYS;
return reset_handler->prepare_hwcontext(adev->reset_cntl,
reset_context);
}
int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
struct amdgpu_reset_context *reset_context)
{
int ret;
struct amdgpu_reset_handler *reset_handler = NULL;
if (adev->reset_cntl)
reset_handler = adev->reset_cntl->get_reset_handler(
adev->reset_cntl, reset_context);
if (!reset_handler)
return -ENOSYS;
ret = reset_handler->perform_reset(adev->reset_cntl, reset_context);
if (ret)
return ret;
return reset_handler->restore_hwcontext(adev->reset_cntl,
reset_context);
}
void amdgpu_reset_destroy_reset_domain(struct kref *ref)
{
struct amdgpu_reset_domain *reset_domain = container_of(ref,
struct amdgpu_reset_domain,
refcount);
if (reset_domain->wq)
destroy_workqueue(reset_domain->wq);
kvfree(reset_domain);
}
struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
char *wq_name)
{
struct amdgpu_reset_domain *reset_domain;
reset_domain = kvzalloc(sizeof(struct amdgpu_reset_domain), GFP_KERNEL);
if (!reset_domain) {
DRM_ERROR("Failed to allocate amdgpu_reset_domain!");
return NULL;
}
reset_domain->type = type;
kref_init(&reset_domain->refcount);
reset_domain->wq = create_singlethread_workqueue(wq_name);
if (!reset_domain->wq) {
DRM_ERROR("Failed to allocate wq for amdgpu_reset_domain!");
amdgpu_reset_put_reset_domain(reset_domain);
return NULL;
}
atomic_set(&reset_domain->in_gpu_reset, 0);
atomic_set(&reset_domain->reset_res, 0);
init_rwsem(&reset_domain->sem);
return reset_domain;
}
void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain)
{
atomic_set(&reset_domain->in_gpu_reset, 1);
down_write(&reset_domain->sem);
}
void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain)
{
atomic_set(&reset_domain->in_gpu_reset, 0);
up_write(&reset_domain->sem);
}
|
